公开(公告)号：WO2021141630A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/041194

申请日：2020-07-08

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： JOERGENSEN, Thomas ,  BRANSCOMB, Brian

IPC: H04J3/06 ,  H04J3/0688 ,  H04J3/0697 ,  H04L49/351 ,  H04L7/0079

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.