公开(公告)号：EP0913766A3

公开(公告)日：1999-12-29

申请号：EP98119376.6

申请日：1998-10-14

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Triece, Joseph W. ,  Mitra, Sumit K.

IPC: G06F9/34

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30192 ,  G06F9/34

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：EP0913766A2

公开(公告)日：1999-05-06

申请号：EP98119376.6

申请日：1998-10-14

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Triece, Joseph W. ,  Mitra, Sumit K.

IPC: G06F9/34

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30192 ,  G06F9/34

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

Abstract translation: 一种用于允许多个寻址模式，同时最大化的多个可用的操作码和寻址的寄存器的系统。 该系统具有用于通过使用虚拟寄存器地址的多个寻址模式的编码允许一个处理器架构方案。 该系统已到指令集具有指令的多个。 每条指令有worin没有在每个指令的多个比特的多个比特的多元化是贯彻不同的寻址模式专用比特。 每一个指令的多个能够通过在ProcessorArchitecture用于方案解决虚拟寄存器地址来实现不同的寻址模式。 由于没有位都需要实现不同的寻址模式，操作码字段的长度和寄存器地址字段是确定性的由操作码的数量和可寻址寄存器中的用户希望实现的数量开采。

公开(公告)号：EP0908812A3

公开(公告)日：1999-12-08

申请号：EP98118314.8

申请日：1998-09-28

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Mitra, Sumit K. ,  Triece, Joseph W.

IPC: G06F9/35

CPC classification number: G06F9/30138 ,  G06F9/35

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract translation: 处理器体系结构方案允许通过使用虚拟寄存器地址来编码多种寻址模式，以便在处理器体系结构方案中最大化可直接寻址的寄存器的数量。 在存储器中保留与间接寻址指针相关联的一组虚拟地址寄存器位置。 保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的多个间接寻址模式。 当访问时，每个虚拟寄存器地址位置启动间接寻址模式以与相关的间接寻址指针一起使用。

公开(公告)号：EP0913766B1

公开(公告)日：2002-08-28

申请号：EP98119376.6

申请日：1998-10-14

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Triece, Joseph W. ,  Mitra, Sumit K.

IPC: G06F9/34 ,  G06F9/35

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30192 ,  G06F9/34

公开(公告)号：EP0908812B1

公开(公告)日：2002-04-03

申请号：EP98118314.8

申请日：1998-09-28

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Mitra, Sumit K. ,  Triece, Joseph W.

IPC: G06F9/35

CPC classification number: G06F9/30138 ,  G06F9/35

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

公开(公告)号：EP0908812A2

公开(公告)日：1999-04-14

申请号：EP98118314.8

申请日：1998-09-28

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Mitra, Sumit K. ,  Triece, Joseph W.

IPC: G06F9/35

CPC classification number: G06F9/30138 ,  G06F9/35

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract translation: 一种处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码，以便最大化处理器架构方案中直接可寻址寄存器的数量。 与间接寻址指针相关联的一组虚拟地址寄存器位置在存储器中保留。 保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的间接寻址模式的数量。 每个虚拟寄存器地址位置启动在访问时与相关联的间接寻址指针一起使用的间接寻址模式。