公开(公告)号：EP1000439A1

公开(公告)日：2000-05-17

申请号：EP99918816.2

申请日：1999-04-23

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： ST. AMAND, Roger ,  MA, Robert ,  DEUTSCHER, Neil

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/314

CPC classification number: H01L21/3145 ,  H01L21/32 ,  H01L21/76202

Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

公开(公告)号：EP1000439B1

公开(公告)日：2006-12-13

申请号：EP99918816.2

申请日：1999-04-23

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： ST. AMAND, Roger ,  MA, Robert ,  DEUTSCHER, Neil

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/314

CPC classification number: H01L21/3145 ,  H01L21/32 ,  H01L21/76202

Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.