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    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL
    2.
    发明申请
    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL 有权

    公开(公告)号：US20230024167A1

    公开(公告)日：2023-01-26

    申请号：US17590650

    申请日：2022-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G06F3/06

    Abstract: A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.

    MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS
    3.
    发明申请
    MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS 有权

    公开(公告)号：US20220208273A1

    公开(公告)日：2022-06-30

    申请号：US17382619

    申请日：2021-07-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Umberto Siciliani ,  Floriano Montemurro ,  Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

    Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

    APPARATUSES AND METHODS FOR AUTOMATED DYNAMIC WORD LINE START VOLTAGE
    5.
    发明申请
    APPARATUSES AND METHODS FOR AUTOMATED DYNAMIC WORD LINE START VOLTAGE 有权

    公开(公告)号：US20210057031A1

    公开(公告)日：2021-02-25

    申请号：US17090067

    申请日：2020-11-05

    Applicant: Micron Technology, Inc.

    Inventor： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

    IPC: G11C16/08 ,  G11C16/12 ,  G06F3/06 ,  G11C8/08

    Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

    Resumption of program or erase operations in memory
    6.
    发明授权
    Resumption of program or erase operations in memory 有权

    公开(公告)号：US12300332B2

    公开(公告)日：2025-05-13

    申请号：US18369479

    申请日：2023-09-18

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G11C16/26 ,  G11C7/10 ,  G11C16/10 ,  G11C16/34

    Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

    Independent plane architecture in a memory device
    7.
    发明授权
    Independent plane architecture in a memory device 有权

    公开(公告)号：US12271592B2

    公开(公告)日：2025-04-08

    申请号：US17887940

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

    IPC: G11C13/00 ,  G06F3/06

    Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

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