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    VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS
    1.
    发明申请
    VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS 审中-公开

    公开(公告)号：WO2021158522A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2021/016176

    申请日：2021-02-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： HOLLIS, Timothy, M. ,  REHMEYER, James, S. ,  CHOI, Baekkyu ,  SHARMA, Yogesh ,  STAVE, Eric, J. ,  HUBER, Brian, W. ,  WISCOMBE, Miles, S.

    IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G06F3/06

    Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

    CHANNEL MODULATION FOR A MEMORY DEVICE
    2.
    发明申请
    CHANNEL MODULATION FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：WO2020150435A1

    公开(公告)日：2020-07-23

    申请号：PCT/US2020/013818

    申请日：2020-01-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： BROX, Martin ,  MAYER, Peter ,  SPIRKL, Wolfgang, Anton ,  HEIN, Thomas ,  RICHTER, Michael, Dieter ,  HOLLIS, Timothy, M. ,  GREEFF, Roy, E.

    IPC: G06F13/16 ,  G06F11/10 ,  G11C7/10

    Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

    FRACTIONAL-RATE DECISION FEEDBACK EQUALIZATION USEFUL IN A DATA TRANSMISSION SYSTEM
    3.
    发明申请
    FRACTIONAL-RATE DECISION FEEDBACK EQUALIZATION USEFUL IN A DATA TRANSMISSION SYSTEM 审中-公开
    数据传输系统中有用的分数率决策反馈均衡

    公开(公告)号：WO2009005941A2

    公开(公告)日：2009-01-08

    申请号：PCT/US2008/065843

    申请日：2008-06-05

    Applicant: MICRON TECHNOLOGY, INC. ,  HOLLIS, Timothy, M.

    Inventor： HOLLIS, Timothy, M.

    IPC: G11C11/407

    CPC classification number: H03K3/356113 ,  H03K5/082 ,  H04L25/03057

    Abstract: Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one- half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously- detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.

    Abstract translation: 公开了判决反馈均衡（DFE）电路用于频率小于数据信号的分数率时钟。 例如，一个半速率钟控DFE电路利用两个输入数据路径，它们分别在关联的半速率时钟的上升沿和下降沿被激活。 每个输入数据路径都有一对具有不同参考电压电平的比较器。 每个输入数据路径中的比较器输出到多路复用器，该多路复用器根据先前接收的比特的逻辑电平在两个比较器输出之间进行选择。 每个输入数据路径的输出作为控制输入发送到另一个数据路径的多路复用器。 因此，即使同步时钟是数据频率的一半，先前检测到的位的结果也会影响哪个比较器的输出传递到电路的输出。 还公开了四分之一速率DFE电路，其操作类似。

    BALANCED DATA BUS INVERSION
    4.
    发明申请
    BALANCED DATA BUS INVERSION 审中-公开
    平衡数据总线反相

    公开(公告)号：WO2009051991A2

    公开(公告)日：2009-04-23

    申请号：PCT/US2008/079131

    申请日：2008-10-08

    Applicant: MICRON TECHNOLOGY, INC. ,  HOLLIS, Timothy, M.

    Inventor： HOLLIS, Timothy, M.

    IPC: G06F13/38

    CPC classification number: H03M5/145 ,  G11C7/1006 ,  H03M7/14

    Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the "balance" of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

    Abstract translation: 公开了一种使用数据总线反转平衡输出负载的方法和装置。 简而言之，一种这样的技术包括测量跨数据总线的数据位的“平衡”（例如，与一组并行数据位中的一个值的数量相比较的零值的数量）。 如果数据位不平衡指定量，数据总线上的位的一部分被反转，并且发送包括反转部分的数据位。 此外，数据总线反相位被设置为特定值并且与数据位一起发送以指示使用数据总线反转。 如果数据信号不是不平衡的（即，数据总线上的位不包括不平衡数量的逻辑值），则数据总线上的位在被检测到时被传输，数据总线反相位被设置为 另一个特殊的值表示没有使用数据总线反转。

    TWO-BIT TRI-LEVEL FORCED TRANSITION ENCODING
    5.
    发明申请
    TWO-BIT TRI-LEVEL FORCED TRANSITION ENCODING 审中-公开
    两位三角强制转换编码

    公开(公告)号：WO2008147631A1

    公开(公告)日：2008-12-04

    申请号：PCT/US2008/062448

    申请日：2008-05-02

    Applicant: MICRON TECHNOLOGY, INC. ,  HOLLIS, Timothy, M.

    Inventor： HOLLIS, Timothy, M.

    IPC: H03M5/00

    CPC classification number: H03M5/16

    Abstract: An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to- zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between '-1 ' and '0' logic states, or '+1 ' and '0' logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.

    Abstract translation: 公开了一种编码技术，用于通过至少每两个数据位强制数据转换来减轻对符号间干扰（ISI）和DC蠕变的影响。 原始非归零（NRZ）数据流中的两个连续比特数据被分组，并由编码电路转换成与原始位相同持续时间的两个新的连续数据位。 每组中的新编码位将必然在三种可能的数据状态中的两种之间转换，具体将在'-1'和'0'逻辑状态之间转换，或'+1'和'0'逻辑状态。 根据该编码方案，不超过两个连续的编码比特将永远是相同的逻辑状态，这防止任何特定数据状态占主导并引起DC蠕变。

    REFERENCE VOLTAGE GENERATION FOR SINGLE-ENDED COMMUNICATION CHANNELS
    6.
    发明申请
    REFERENCE VOLTAGE GENERATION FOR SINGLE-ENDED COMMUNICATION CHANNELS 审中-公开
    单向通信通道的参考电压发生

    公开(公告)号：WO2010085408A1

    公开(公告)日：2010-07-29

    申请号：PCT/US2010/020973

    申请日：2010-01-14

    Applicant: MICRON TECHNOLOGY, INC. ,  DIMITRIU, Dragos ,  HOLLIS, Timothy, M.

    Inventor： DIMITRIU, Dragos ,  HOLLIS, Timothy, M.

    IPC: G11C5/14

    CPC classification number: G05F3/08 ,  H03K19/0175

    Abstract: An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq.

    Abstract translation: 公开了一种改进的参考电压（Vref）发生器，可用于例如感​​测单端通道上的数据。 Vref发生器可以放置在包含接收器的集成电路上，或者可以放在芯片外。 在一个实施例中，Vref发生器包括与电流源组合的可调电阻分压器。 分压器参考I / O电源Vddq和Vssq，其中Vref在分压器的可调电阻之间的节点处产生。 电流源将电流注入到Vref节点中，并将其分成由分压器中使用的相同电阻器形成的不变的戴维南等效电阻。 所产生的电压等于两个项的和：包括Vref和Vddq之间的斜率的第一项，以及包括Vref偏移的第二项。 这些术语中的每一个可以在第一和第二模式中独立调整：通过分压器的斜率项，以及偏移项由注入电流的大小。 在一个有用的实现中使用所公开的Vref发生器允许在Vddq的两个不同值处优化Vref。

    METHOD AND APPARATUS FOR TRAINING REFERENCE VOLTAGE LEVEL AND DATA SAMPLE TIMING IN A RECEIVER
    7.
    发明申请
    METHOD AND APPARATUS FOR TRAINING REFERENCE VOLTAGE LEVEL AND DATA SAMPLE TIMING IN A RECEIVER 审中-公开
    用于在接收器中训练参考电压电平和数据采样时序的方法和装置

    公开(公告)号：WO2009058529A1

    公开(公告)日：2009-05-07

    申请号：PCT/US2008/079165

    申请日：2008-10-08

    Applicant: MICRON TECHNOLOGY, INC. ,  HOLLIS, Timothy, M.

    Inventor： HOLLIS, Timothy, M.

    IPC: G06F13/00

    CPC classification number: H04L7/0054 ,  H04L25/061

    Abstract: Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached.

    Abstract translation: 公开了用于计算接收机系统的最佳采样点的位置的方法和装置。 简而言之，第一种方法包括确定接收信号的最大电压余量和最大定时裕度，并从这些余量确定包括参考电压电平（Vref）和相对采样相位的最佳采样点。 最佳采样点的位置基于最大电压裕度的采样点和最大定时裕度的采样点的位置。 第二种方法包括建立初始采样点，然后连续地对采样点的每个电压和定时分量进行精细化，直到达到最佳采样点。

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