公开(公告)号：WO2016112149A1

公开(公告)日：2016-07-14

申请号：PCT/US2016/012412

申请日：2016-01-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay ,  WHEELER, Kyle, B.

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4091 ,  G11C11/4096 ,  G11C19/28 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/007

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

Abstract translation: 本公开的示例提供了用于确定存储器中最长元素的长度的装置和方法。 示例性方法包括：使用控制器来控制感测电路，存储在存储器阵列中的矢量的多个可变长度元素中的最长元素的长度。

公开(公告)号：WO2016036906A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/048229

申请日：2015-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C16/00 ,  G11C29/00 ,  G11C8/06

CPC classification number: G11C7/10 ,  G06F7/00 ,  G06F7/535 ,  G06F9/3001 ,  G06F12/02 ,  G06F12/0207 ,  G11C7/1006

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了与在存储器中执行分割操作相关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储分红元件的第一组存储器单元。 示例性设备可以包括耦合到第二接入线路并被配置为存储除数元素的第二组存储器单元。 示例性装置还可以包括控制器，其被配置为通过控制感测电路来执行多个操作而不经由输入/输出（I / O）线传送数据来使除数元素被除数元素分割。

公开(公告)号：WO2016036599A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/047467

申请日：2015-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G06F7/523 ,  G06F2207/4802 ,  G11C7/1006 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了用于在存储器中执行乘法运算的装置和方法。 一个示例性方法包括对存储在耦合到存储器阵列的一组存储器单元和多个存储器阵列的感测线的存储器单元中的第一元件和存储在耦合到第二存储器单元的存储器单元组中的第二元件执行乘法运算 访问线和存储器阵列的感测线的数量。 该方法可以包括在不经由输入/输出（I / O）线路传送数据的情况下执行的数字操作。

公开(公告)号：WO2017139191A1

公开(公告)日：2017-08-17

申请号：PCT/US2017/016425

申请日：2017-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： ZAWODNY, Jason T. ,  TIWARI, Sanjay ,  MURPHY, Richard C.

IPC: G11C7/06 ,  G11C7/10 ,  G06F12/08

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Abstract translation: 本公开的实例提供用于将第一元件存储在耦合到第一感测线和多个存取线的存储器单元中的装置和方法。 这些示例可以包括将第二元件存储在耦合到第二传感线和多个存取线的存储器单元中。 耦合到第一感测线的存储器单元可以通过至少耦合到第三感测线的存储器单元和耦合到第二感测线的存储器单元与多个存取线分开。 这些示例可以包括将第二元件存储在耦合到第三传感线的存储单元中。

公开(公告)号：WO2016144951A1

公开(公告)日：2016-09-15

申请号：PCT/US2016/021359

申请日：2016-03-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C7/06 ,  G11C7/22

CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了用于在存储器中执行移位操作的装置和方法。 一个示例性方法包括执行移位操作，该第一元素存储在耦合到第一存取线的第一组存储器单元和存储器阵列的多条感测线以及存储在耦合到第一存储器单元的第二组存储器单元中的第二元件 第二访问线和存储器阵列的感测线的数量。 该方法可以包括通过执行不经由输入/输出（I / O）传送数据而执行的多个AND运算，OR运算，SHIFT运算和INVERT运算，来移动第一元素移动由第二元素限定的位数位置。 线。

公开(公告)号：WO2016036912A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/048248

申请日：2015-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C7/06 ,  G11C7/10 ,  G06F12/02

CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/12 ,  G11C8/10

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

Abstract translation: 本公开包括与在存储器中执行比较操作有关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储多个第一元件的第一组存储器单元，以及耦合到第二接入线路并被配置为存储多个第二元件的第二组存储器单元。 该装置可以包括：控制器，被配置为通过控制感测电路来执行多个操作而不经由输入/输出（I / O）线传输数据，使多个第一元件与多个第二元件进行比较， 可以并行地比较多个第一元件和多个第二元件。

公开(公告)号：WO2016036602A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/047488

申请日：2015-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G06F7/523 ,  G06F7/53 ,  G06G7/16 ,  G11C7/1006 ,  G11C11/4091 ,  H03K19/17732

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了用于在存储器中执行乘法运算的装置和方法。 示例性方法包括对第一向量和第二向量执行乘法运算。 第一矢量包括存储在耦合到存储器阵列的第一存取线和多条感测线的一组存储器单元中的多个第一元件。 第二向量包括存储在耦合到第二访问线的一组存储器单元中的多个第二元件和存储器阵列的感测线的数量。 示例性乘法运算可以包括执行多个AND运算，或运算和SHIFT运算，而不经由输入/输出（I / O）线传输数据。

公开(公告)号：WO2015187902A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/034103

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C29/1201 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/785 ,  G11C7/065 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C16/10 ,  G11C29/14 ,  G11C29/32 ,  Y02D10/13

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了与在存储器中执行比较操作有关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储第一元件的第一组存储器单元。 示例性设备还可以包括耦合到第二接入线路并被配置为存储第二元件的第二组存储器单元。 示例性装置还可以包括感测电路，其被配置为通过在不经由输入/输出（I / O）线路传送数据的情况下执行多个AND运算，OR运算，SHIFT运算和INVERT运算来比较第一元件与第二元件。