公开(公告)号：MY186464A

公开(公告)日：2021-07-22

申请号：MYPI2012005435

申请日：2012-12-14

Applicant: MIMOS BERHAD

Inventor： MOHD SHAFIQ BIN ALIAS ,  DR ETTIKAN KANDASAMY KARUPPIAH ,  DR ONG HONG HOE ,  SHAHIRINA BINTI MOHD TAHIR

Abstract: The present invention provides a system for synchronising memory data transfer. The system comprises a host Central Processing Unit (CPU) (202) having a memory optimizer (221); and a Field Programmable Gate Array (FPGA) (204) having a memory load identifier (225). When data is received on the host CPU, the memory optimizer (221) is adapted to operationally check memory utilization (625) at an idle state in the FPGA (204) and determine whether to drop/retain data based on the memory utilization on the FPGA (204); and when data is processed on the FPGA (204), the memory load identifier (255) is adapted to operationally check memory utilization at an idle sate in the host CPU and determine whether to drop/retain data based on the memory utilization on the host CPU. A method of synchronizing memory data is also provided herewith.