公开(公告)号：MY192587A

公开(公告)日：2022-08-29

申请号：MYPI2018001448

申请日：2018-08-15

Applicant: MIMOS BERHAD

Inventor： TAN KONG YEW ,  ROHAYA BINTI ABDUL WAHAB

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: The present invention discloses a method of building a binary weighted split capacitor array (1) for minimizing routing induced parasitic mismatch. Specifically, the binary weighted split capacitor array is built with a plurality of unit capacitors with three- dimensional structures having a top plate comprising a plurality of stacked metal plates (M2, M3, M4, M5) and a bottom plate enclosing the top plate with side walls, a floor layer and a ceiling layer to minimize top plate parasitic capacitance to the substrate, and to achieve overall equal parasitic capacitance to the substrate. (Figure 15)

公开(公告)号：MY173761A

公开(公告)日：2020-02-19

申请号：MYPI2014002910

申请日：2014-10-13

Applicant: MIMOS BERHAD

Inventor： ROHAYA BINTI ABDUL WAHAB ,  RAJA MOHD FUAD BIN TENGKU AZIZ ,  NAZALIZA BINTI OTHMAN

Abstract: There is provided a system adapted for providing automated operation of locating or detecting antenna violations areas and fixing the areas affected by said antenna violations based on design rule checking (DRC) data and layout data The system includes an analyzer (10) which is accordingly configured to analyze the DRC data and layout data of the IC and automatically obtains locations of areas including metal layers affected by the antenna violations and generating an output based on the analysis; and a fixer (11) configured to be in communication with the analyzer (10); whereby the fixer (11) utilizes the output from analyzer (10) to automatically insert metal jumper and at least one via within the IC; and then updating the layout data of the IC. A method for automatically locating and fixing antenna violations in integrated circuits (IC) is also provided.