公开(公告)号：EP2061080A4

公开(公告)日：2011-03-23

申请号：EP07743504

申请日：2007-05-16

Applicant: MITSUI HIGH TEC

Inventor： MATSUNAGA KIYOSHI ,  SHIOYAMA TAKAO ,  HIRASHIMA TETSUYUKI

IPC: H01L21/48 ,  H01L23/495 ,  H01L25/10

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device 10 includes a semiconductor element 12; a group of back-inner terminals 14 coupled with the semiconductor element 12 through bonding wires 13 and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals 15 arranged outside the group of back-inner terminals 14; a group of front-outer terminals 17 located immediately above the back-outer terminals 15 to be exposed from the front surface, which are electrically coupled with the back-outer terminals 15 located immediately therebelow through coupling conductors 16, respectively; and a sealing resin 18 which seals the semiconductor element 12 and bonding wires 13 and non-exposed portions of said back-inner terminals 14, back-outer terminals 15 and front-outer terminals 17. On at least the respective terminal faces of said back-inner terminals 14, back-outer terminals 15 and front-outer terminals 17, noble-metal plated layers 19, 19b are formed.

公开(公告)号：EP1947692A4

公开(公告)日：2010-08-04

申请号：EP06823100

申请日：2006-11-07

Applicant: MITSUI HIGH TEC

Inventor： MATSUNAGA KIYOSHI ,  MIMURA CHIKAYA ,  SHIOYAMA TAKAO

IPC: H01L23/50

CPC classification number: H01L23/49537 ,  H01L21/4842 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49222 ,  H01L2924/00

公开(公告)号：JP2012049323A

公开(公告)日：2012-03-08

申请号：JP2010189797

申请日：2010-08-26

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： MATSUNAGA KIYOSHI ,  SHIOYAMA TAKAO ,  HIRASHIMA TETSUYUKI

IPC: H01L23/50 ,  H01L23/12

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a lead frame which can minimize degradation in quality of a product by preventing a terminal from coming out of resin, and to provide a method of manufacturing the same.SOLUTION: A lead frame 16 is provided, on one side thereof, with a wire bonding portion 13 having a first plating part 12 formed on the surface and, on the other side thereof, with an external connection terminal 15 corresponding to the wire bonding portion 13 and having a second plating part 14 formed on the surface. The first plating part 12 is projected from around the tip of the wire bonding portion 13 and the thickness T1 of the first plating part 12 excepting a noble metal plating layer is set in the range of 5-50 μm before forming a first stopper 23 around the tip of the wire bonding portion 13. In the manufacturing method, the first plating part 12 is formed by applying thick plating 26 to the pointed end face of a wire bonding portion 13 to be formed, and then etching a lead frame material 20. A semiconductor device 10 uses this lead frame 16.

Abstract translation: 要解决的问题：提供一种引线框架，其可以通过防止端子从树脂中脱出而使产品的质量降低最小化，并提供其制造方法。 解决方案：引线框架16的一侧设置有引线接合部分13，引线接合部分13具有形成在表面上的第一电镀部分12，并且在另一侧具有对应于外部连接端子15的外部连接端子15。 引线接合部分13并且具有形成在表面上的第二电镀部分14。 第一电镀部12从引线接合部13的前端突出，除了贵金属电镀层之外，第一电镀部12的厚度T1在形成第一止动件23之前设定在5-50μm的范围内 导线接合部分13的尖端。在制造方法中，通过将厚镀层26施加到待形成的引线接合部分13的尖端面上，然后蚀刻引线框架材料20来形成第一电镀部分12。 半导体器件10使用该引线框架16.版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2010040596A

公开(公告)日：2010-02-18

申请号：JP2008198902

申请日：2008-07-31

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： MATSUNAGA KIYOSHI ,  KUBO KIMIHIKO

IPC: H01L23/50 ,  H01L23/12

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a laminated lead frame that meets diffusion bonding conditions of a laminated lead frame having no plating layer formed.
SOLUTION: The laminated lead frame is constituted by applying predetermined form-shaping to each of a lead frame material and a lead frame material for lamination (a conductor plate 16 and a surface outside terminal 17), and bonding the lead frame material for lamination on the form-shaped lead frame material, wherein a surface of the lead frame material made of copper or copper alloy is coated with an copper oxide layer C of ≥0.1 μm in thickness. The copper oxide layer formed on the lead frame material prevents a brittle copper oxide coating film from being formed, and tight adhesiveness between the lead frame material and the formed copper oxide layer improves reliability of a semiconductor device.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种满足不形成镀层的叠层引线框架的扩散接合条件的层叠引线框架。 解决方案：层叠引线框架通过对引线框架材料和用于层叠的引线框架材料（导体板16和表面外部端子17）施加预定的成形形状而构成，并且将引线框架材料 用于层叠在形状的引线框架材料上，其中由铜或铜合金制成的引线框架材料的表面涂覆有厚度≥0.1μm的氧化铜层C. 形成在引线框架材料上的氧化铜层防止形成脆性氧化铜涂层，引线框架材料和形成的氧化铜层之间的紧密粘合性提高了半导体器件的可靠性。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009164232A

公开(公告)日：2009-07-23

申请号：JP2007340199

申请日：2007-12-28

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： MATSUNAGA KIYOSHI ,  MORI SHUJI

IPC: H01L23/50 ,  H01L23/12

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which uses a plating material that can reduce cost, on a terminal face of at least a substrate-side mounting surface to permit application of thick plating and can form an oxidation preventive film on the side surface of a mounting-side terminal, and to provide a manufacturing method thereof, as well as a lead frame and a manufacturing method thereof. SOLUTION: The semiconductor device is provided with a semiconductor element 11, columnar terminals 14 arranged like an area array in its periphery, and a bonding wire 16 which electrically connects an electrode pad 15 of the semiconductor pad 11 with a wire bonding part 12 of the columnar terminals 14. The semiconductor element 11, the bonding wire 16 and a part of the columnar terminals 14 are packaged by a resin, and a part of each of the columnar terminals 14 is projected from the lower end of the sealing resin 17, and then each of the columnar terminals 14 is formed by half etching from the front side and rear side, respectively. Gold plating 23 is applied onto the upper surface of the respective columnar terminals 14, and tin plating 25 or solder plating made mainly of tin is applied onto the lower surface of the respective columnar terminals 14 projecting from the sealing resin 17. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供使用能够降低成本的电镀材料的半导体器件，在至少基板侧安装面的端子面上，以允许施加厚电镀并且可以形成氧化防止膜 安装侧端子的侧面，以及其制造方法以及引线框及其制造方法。 解决方案：半导体器件设置有半导体元件11，在其周边排列成像区域阵列的柱状端子14以及将半导体焊盘11的电极焊盘15与引线接合部分电连接的接合线16 12个柱状端子14.半导体元件11，接合线16和一部分柱状端子14由树脂封装，并且每个柱状端子14的一部分从密封树脂的下端突出 然后，分别从前侧和后侧通过半蚀刻形成每个柱状端子14。 在各个柱状端子14的上表面上涂敷金镀层23，在从密封树脂17突出的各柱状端子14的下表面上涂敷镀锡25或主要由锡形成的焊锡镀层。 （C）2009，JPO＆INPIT

公开(公告)号：JP2009164149A

公开(公告)日：2009-07-23

申请号：JP2007338972

申请日：2007-12-28

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： MATSUNAGA KIYOSHI ,  SHIOYAMA TAKAO

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve strength, prevent short-circuit, improve mounting property and suppress deformation in such a semiconductor device on the lower-layer side that constitutes a laminated semiconductor package, and to provide a manufacturing method thereof.
SOLUTION: The semiconductor device is provided with: a wire section 13s which is formed at the upper central area of a resin mold and of which the thickness from the bottom of the resin mold is made larger than a height of a loop of a bonding wire; a connection terminal section 13t which is formed around the wire section 13s and of which the thickness from the bottom of the resin mold is made smaller than that of the wire section 13s; and a reinforced surrounding wall section 13w which is formed in the periphery of the connection terminal section 13t and of which the thickness from the bottom of the resin mold is made the same as that of the wire section 13s.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体器件，其可以提供强度，防止短路，提高安装性能并抑制构成层叠半导体封装的下层侧的这种半导体器件中的变形，并且提供 其制造方法。 解决方案：半导体器件设置有：线部分13s，其形成在树脂模具的上中心区域，其中来自树脂模具的底部的厚度大于环路的高度 接合线; 连接端子部13t，其形成在线部分13s周围，并且其厚度来自树脂模具的底部的厚度小于线部分13s的厚度; 以及形成在连接端子部13t的周围的加强围壁部13w，其与树脂模的底部的厚度形成为与导线部13s的厚度相同。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009049173A

公开(公告)日：2009-03-05

申请号：JP2007213594

申请日：2007-08-20

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： MATSUNAGA KIYOSHI ,  MORI SHUJI

IPC: H01L23/12 ,  H01L21/56 ,  H01L23/50

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method forming a post at the semiconductor device assembling step.
SOLUTION: A metallic mold 30 with a protrusion in a position corresponding to a connection terminal 14 is superposed on a lead frame material 20 and a sealing resin 12 is poured into the mold to seal with the resin. A metal paste 24 such as solder is poured into a hole 23 formed after removing the metallic mold 30 and the resin is cured at a fusing temperature of the metal paste 24 to form the post 17 on the connection terminal 14.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供在半导体器件组装步骤中形成柱的半导体器件及其制造方法。 解决方案：将具有与连接端子14相对应的位置的突起的金属模具30重叠在引线框架材料20上，并将密封树脂12注入到模具中以与树脂密封。 将金属糊料24（例如焊料）倒入到去除金属模具30之后形成的孔23中，并且树脂在金属膏24的熔合温度下固化，以在连接端子14上形成柱17。版权所有： （C）2009，JPO＆INPIT

公开(公告)号：JP2001101366A

公开(公告)日：2001-04-13

申请号：JP27631699

申请日：1999-09-29

Applicant: MITSUI HIGH TEC

Inventor： MATSUNAGA KIYOSHI

IPC: G06K19/07 ,  G06K19/077 ,  H01Q1/38 ,  H01Q7/00

Abstract: PROBLEM TO BE SOLVED: To provide an antenna circuit substrate manufacturing method for obtaining an antenna substrate which is high in productivity, reduces costs and has the good shape of an antenna circuit pattern. SOLUTION: This antenna substrate manufacturing method makes the cutting of an antenna circuit pattern at a metallic foil 21 with a half cut blade 24 through a substrate 1 provided with the foil 21 through an adhesive 22 between a role, which is provided with the blade 24 projectingly provided at the pattern of an antenna circuit pattern and a full cut blade 25 for making cutting also at the substrate 1, and a supporting role, cuts the outline of the antenna substrate 1 by the blade 25 and next, separates the foil 21 at a part except for the antenna circuit pattern from the substrate 1 to form the antenna circuit pattern. After forming the antenna circuit pattern, UV is additionally irradiated to harden the adhesive between the metallic foil and the substrate.

公开(公告)号：JP2000254897A

公开(公告)日：2000-09-19

申请号：JP5799499

申请日：1999-03-05

Applicant: MITSUI HIGH TEC

Inventor： MATSUNAGA KIYOSHI ,  MORITA TAKESHI

IPC: B26F1/00 ,  B26F1/44

Abstract: PROBLEM TO BE SOLVED: To save a time require for polishing and to improve productivity, in the blade of a cutter used for a manufacturing method to perform half cut and full cut of a multilayer tape at the same process. SOLUTION: In the blade 1 of a cutter for forming a tape used for manufacture of a tape that a multilayer tape material 4 is half-cut or full-cut at the same process, and a cut blade part 3 for half-cut and a cut blade part 2 for full cut are individually formed to be combined into the single edge 1. This constitution, since only a necessary cut blade part can be polished, eliminates a need to re-grind all the edge and shortens a regulation time.

公开(公告)号：JP2008071815A

公开(公告)日：2008-03-27

申请号：JP2006246990

申请日：2006-09-12

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： MATSUNAGA KIYOSHI ,  SHIOYAMA TAKAO ,  HIRASHIMA TETSUYUKI

IPC: H01L23/50 ,  H01L23/12 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer multichip modular semiconductor device, a lead frame product for use in the semiconductor device, and a process for manufacturing the semiconductor device. SOLUTION: The semiconductor device 10 has a semiconductor element 12, a group of inner back side terminals 14 coupled with the semiconductor element 12 through a bonding wire 13 and arranged in area array while being exposed to the inside of the footprint, a group of outer back side terminals 15 formed on the outside of the group of inner back side terminals 14 contiguously thereto, a group of outer surface side terminals 17 located directly above the outer back side terminals 15 while being exposed to the surface and coupled electrically with the outer back side terminals 15 directly under through a coupling conductor 16, and resin 18 for sealing the unexposed part of the semiconductor element 12, the bonding wire 13, each inner back side terminal 14, each outer back side terminal 15 and each outer surface side terminal 17 wherein noble metal plating layers 19 and 19b are formed on the respective terminal surfaces of at least the inner back side terminal 14, the outer back side terminal 15 and the outer surface side terminal 17. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种多层多芯片模块化半导体器件，用于半导体器件的引线框架产品以及半导体器件的制造工艺。 解决方案：半导体器件10具有半导体元件12，一组内侧侧端子14，其通过接合线13与半导体元件12耦合，并且在暴露于占位面的内部的同时以面阵列布置， 一组外侧端子15，形成在与其相邻的内侧后端子端子组14的外侧;一组外表面侧端子17，位于外侧端子15的正上方，同时暴露于表面并与 通过耦合导体16正下方的外侧背面端子15以及用于密封半导体元件12的未曝光部分，接合线13，内侧后端子端子14，各外侧后端子端子15以及各外表面的树脂18 侧端子17，其中贵金属镀层19和19b形成在至少内侧后端子端子14，外侧背面端子 小号15和外表面侧终端17.版权所有（C）2008，JPO＆INPIT