公开(公告)号：JP2007150372A

公开(公告)日：2007-06-14

申请号：JP2007067330

申请日：2007-03-15

Applicant: Mitsui High Tec Inc ,  株式会社三井ハイテック

Inventor： NAKAJIMA TAKASHI

IPC: H01L23/50

CPC classification number: H01L2224/48247 ,  H01L2224/73265

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured at relatively low cost.
SOLUTION: A semiconductor element 11 is disposed in the center. A conductive terminal 14 having an upper surface side which acts as a wire bonding portion 12 and having a lower surface side which acts as an external connection terminal portion 13 is disposed in an area array around the semiconductor element 11. The wire bonding portion 12 is electrically connected to a corresponding electrode pad 15 on the semiconductor element 11 by a bonding wire 16. The semiconductor element 11, the bonding wire 16, and the upper half of the conductive terminal 14 are resin-sealed by a seal resin 18.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供可以以相对低的成本制造的半导体器件。 解决方案：半导体元件11设置在中心。 具有作为引线接合部分12的上表面侧并具有用作外部连接端子部分13的下表面侧的导电端子14布置在围绕半导体元件11的区域阵列中。引线接合部分12是 通过接合线16与半导体元件11上的对应的电极焊盘15电连接。半导体元件11，接合线16以及导体端子14的上半部分由密封树脂18树脂密封。

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公开(公告)号：JP2001053195A

公开(公告)日：2001-02-23

申请号：JP22777799

申请日：1999-08-11

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L23/12 ,  H01L21/56

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device at a wafer level, capable of manufacturing at a comparatively low cost without performing thick plating. SOLUTION: In this semiconductor device, a wafer 10, on which a plurality of integrated circuits are formed, and a lead frame 14 in which protrusions 13, corresponding to electrode pads 11 of the respective integrated circuits are formed on one surface side by half etching are prepared, and the electrode pads 11 of the integrated circuits formed on the wafer 10 are connected electrically with the protrusions 13 of the lead frame 14. Resin sealing of at least the bonding part of the wafer 10 and the lead frame 14 is performed, and unwanted parts of the other surface side of the lead frame 14 are eliminated by etching, and protruded terminal parts 16 are formed. After that, the sizing of the wafer 10 is performed for every semiconductor device 17.

公开(公告)号：JP2000100841A

公开(公告)日：2000-04-07

申请号：JP28591898

申请日：1998-09-21

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L21/56 ,  B29C45/14 ,  B29L31/34

Abstract: PROBLEM TO BE SOLVED: To prevent the planarity of an inner lead from being dispersed and to prevent the occurrence of resin flare on an exposed face at molding by clamping a part of the exposed inner lead and molding it. SOLUTION: An exposure face 6 of an inner lead 7 is depressed to a lower die 12 with a first upper die 11, and an inner lead exposure part 10 containing the inner end 13 of the inner lead exposure part 10 is clamped. A first molding process for sealing a pad 2, a semiconductor chip 1, a wire 4, the inner lead 7 containing a bend part 14 except for the exposure part and an inner lead tip 3 and the pad 2 except for the exposure face with resin, is executed. Then an outer lead is clamped by a second upper die and a lower die 12, and the inner lead exposure part 10 is sealed with resin. In first molding, the inner lead is fixed, and the inner lead exposure part 10 is molded in a subsequent second molding process. Thus, the occurrence of resin flare on the exposure face 11 of the inner lead 7 is prevented.

公开(公告)号：JPH11233681A

公开(公告)日：1999-08-27

申请号：JP4141298

申请日：1998-02-07

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L23/12 ,  H01L21/60

Abstract: PROBLEM TO BE SOLVED: To provide a metal carrier type semiconductor device, wherein the connection terminals are disposed also on a mounting part of a semiconductor element, the heat dissipation and reinforcing property of the prior art has are maintained, and the size is reduced further. SOLUTION: This device a semiconductor element 15 mounted and secured on an element mount of a metal carrier 14, a plurality of bonding wires respectively forming electrically conductive circuits between electrode pads of the semiconductor element 15 and inner connection types 24 exposed at wire bonding regions formed in through-holes 18 of the metal carrier 14, an encapsulating resin 17 covering at least regions round the electrodes pads 29 of the semiconductor element 15 and bonding wires, and outer connection terminals provided on outer connection terminal lands which project from an insulation sheet to the back side.

公开(公告)号：JPH11233669A

公开(公告)日：1999-08-27

申请号：JP4436698

申请日：1998-02-10

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor device having external connection terminal which can be formed at a small pitch, enabling to surface mounting of the device on a motherboard without causing short-circuiting, and having a superior capability of absorbing a thermal stresses, based on a difference in the thermal expansion coefficient between a semiconductor chip and the motherboard. SOLUTION: In this method for manufacturing a semiconductor device having external connection terminals interposed on a lower side of a semiconductor chip through a insulating layer and a wiring pattern, a first insulating layer 3 is provided on a lower side of a semiconductor chip 1 so as to expose bumps, a wiring pattern 4 and a second insulating layer 5 are sequentially formed on the lower surface, the second insulating layer 5, corresponding to scheduled locations 6 of forming the external connection terminals, a third insulating layer 7 of photosensitive resin such as polyimide or acrylic resin is provided on the second layer 5 as being overlapped therewith, an external connection terminal formation pattern is printed and developed on the third layer 7 to form external connection projections 8, the projections 8 are plated to form a plating layer 9 and a solder plating layer 10 thereon. As a result, a semiconductor device is manufactured having external connection terminals.

公开(公告)号：JPH11168116A

公开(公告)日：1999-06-22

申请号：JP35236997

申请日：1997-12-04

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L21/60

Abstract: PROBLEM TO BE SOLVED: To ensure good bondability of a semiconductor chip to a wiring board by a method, wherein an electrode bump uses a conductive resin as its constituent member, has an Ni-plated layer in its first surface layer, has an Al-plated layer in its second surface layer and is formed in such a way that the bump is formed into a curve, which is formed into a roughly gull-wing form from the point part of the bump towards the peripheral edge part of the bottom of the bump. SOLUTION: A bump 8 is aligned with an electrode pad 10 on a wiring board 9, and the bump 8 is reflowed to bond together a semiconductor chip 1 and the board 9. At this time, since a creamy solder is applied on the pad 10, the solder 11 is sucked up to approximately half the height of the bump 8 and an Au-plated layer 7 is etched, however since the layer 7 is a thin layer, the tender layer of the layer 7 is formed into a small form to the utmost and at the same time, as the solder is bonded to an Ni-plated layer 6 by an anchor effect, the solder is obtained a firm bonded state. Moreover, since the bump 8 has a curve, which is formed into a roughly gull-wing form from the point thereof towards the peripheral edge part of the bottom thereof, this curve part makes a flexible motion for buffering thermal stresses even if the bump 8 is subjected to thermal stresses.

公开(公告)号：JPH0964225A

公开(公告)日：1997-03-07

申请号：JP24090995

申请日：1995-08-25

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L23/12 ,  H01L23/50

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device and lower its cost, by welding two insulation members pressingly on its conductor circuit patterns from both sides of the circuit patterns to maintain the initial shapes and dimensions. SOLUTION: A second insulator layer 26 has a plurality of continuity holes 25 formed to expose a plurality of corresponding external connection terminal lands 24 to the external. Thereby, the separation of a resin sealing member 19 from conductor circuit patterns 13 is prevented. Further, a semiconductor chip mounting board 14 is configured for the conductor circuit patterns 13 to be sandwiched between a first insulator layer 23 and a photo-curing dry-film- photoresist exemplified as the second insulator layer 26. Thereby, the photoresist is filled into the clearances between the conductor circuit patterns 13 and is cured for the circuit patterns 13 to be one with each other and maintain the shapes and dimensions of their initial states.

公开(公告)号：JPH0955447A

公开(公告)日：1997-02-25

申请号：JP22709995

申请日：1995-08-11

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To dispense with a separate ground plane while the multipin structure of a semiconductor device is easy by a method wherein a reinforcing support material for a tape, which is made of a resin and provided with a circuit pattern, is made to have continuity with a prescribed solder ball out of solder balls and is made to function also as a ground plane. SOLUTION: A semiconductor support material 5 for a tape 1, which is made of a resin and provided with a circuit pattern 2, is a metal thin plate, for example, is provided on the side of the upper surface of the pattern 2 via a bonding agent 6, the tape 1 is reinforced by the material 5 and a deformation, such 'as bent, torsion or warpage, is prevented from being generated in the material 5. Solder balls 7 function as external connection terminals, which connect through holes 8, which are provided in prescribed places on the tape 1, with the prescribed circuit pattern 2. Here, an arbitrary solder ball 7a out of the balls 7 is made to have continuity with the material 5 through a through hole 9 formed in the layer of the tape 1 and the agent 6 and the material 5 is made to function also as a ground plane.

公开(公告)号：JPH08264679A

公开(公告)日：1996-10-11

申请号：JP9606495

申请日：1995-03-28

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI ,  TAKAI KEIJI ,  TATEISHI KOJI

IPC: H01L23/12 ,  H01L21/60 ,  H01L21/603 ,  H01L23/10

Abstract: PURPOSE: To eliminate warpage and crack and to improve the reliability in productivity and packaging by using a semiconductor circuit element mounting substrate where a circuit substrate consisting of metal substrate and glass cloth epoxy resin is joined as specified and performing potting resin sealing. CONSTITUTION: A copper metal substrate 12 with improved heat conductivity where a semiconductor circuit element mounting substrate 22 is subjected to nickel plating is used and a semiconductor circuit element 14 is mounted via a conductive adhesive. Also, a circuit substrate 17 consisting of the metal substrate 12 and glass cloth epoxy resin is subjected to thermocompression bonding via a thermosetting prepreg 15a consisting of glass cloth. Then, the semiconductor circuit element 14 is completely covered with and protected by the metal substrate 12. Further, a resin sealing body 26 where at least semiconductor circuit element 14 and a bonding wire 25 are sealed is provided, thus preventing the warpage and release of resin sealing body due to thermal stress and the occurrence of crack and improving productivity and packaging reliability.

公开(公告)号：JPH08222845A

公开(公告)日：1996-08-30

申请号：JP4612395

申请日：1995-02-09

Applicant: MITSUI HIGH TEC

Inventor： NAKAJIMA TAKASHI

IPC: H01L21/60 ,  H01L21/603 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36 ,  H01L21/321

Abstract: PURPOSE: To mount a semiconductor device on a printed board without using solder balls by forming a lead pattern having terminal sections to be joined to the substrate and applying cream solder to the surfaces of the pad sections of the substrate, and then, joining the terminal sections to the pad sections by making the cream solder to reflow. CONSTITUTION: A semiconductor device 10 to be mounted on a printed board 26 is provided with a semiconductor element 11 and a base tape 12 constituting a substrate for mounting the element 11. The tape 12 is provided with lead patterns 14 and 15 on both surfaces of a polyimide resin film 13, etched copper films 16 and 17, and tin plating baths 18 and 19. Each terminal of the patterns 14 and 15 is connected to terminals 22 and 23 through throughholes. Then, after applying cream solder to pads 28 formed on a printed board 2, the semiconductor device 10 is set to a prescribed position on the board 26 and the cream solder applied to the pads 28 is brought into contact with the corresponding terminal sections 22 and 23 and heated in a reflow furnace. Therefore, the mount work of the device 10 can be simplified.