Abstract:
In accordance with the present invention there is those provided a Cartesian loop transmitter having an isolator eliminator circuitry comprising a set of low pass and band pass filters for each of an I- and Q-channels, root mean square detectors and a divider connected to a comparator are received by a microprocessor which controls attenuation setting. There is also provided a method of adjusting an output level of such transmitter. Said method comprises the step of measuring an on-channel signal level and a noise level and then calculating a ratio of said noise to said on-channel signal. If the ratio exceeds a defined threshold an attenuation of the input attenuators is increased.
Abstract:
In accordance with the present invention there is those provided a Cartesian loop transmitter having an isolator eliminator circuitry comprising a set of low pass and band pass filters for each of an I- and Q-channels, root mean square detectors and a divider connected to a comparator are received by a microprocessor which controls attenuation setting. There is also provided a method of adjusting an output level of such transmitter. Said method comprises the step of measuring an on-channel signal level and a noise level and then calculating a ratio of said noise to said on-channel signal. If the ratio exceeds a defined threshold an attenuation of the input attenuators is increased.
Abstract:
When an isolator is not provided between a power amplifier 126 and an antenna 128, reflected power can increase amplifier distortion. Because an isolator is bulky, narrowband and expensive, it is preferred to use instead an isolator eliminator 106 which attenuates the input baseband signals when excessive adjacent channel power is detected in the Cartesian loop error signals. Attenuation is increased in steps, allowing time for settling of the loop, until the ratio of the adjacent channel and on-channel signal amplitudes falls below a threshold. The on-channel and adjacent channel amplitude signals are produced respectively by low-pass 138,142 and bandpass filters 140,144 coupled to root-mean-square detectors 146,148.
Abstract:
An integrated circuit includes a linearizer circuit in which excessive delay is compensated. The linearizer circuit includes a power amplifier, forward and feedback paths, and a microprocessor. A signal from the power amplifier is routed by the forward path to be transmitted while a portion of the signal to be transmitted is routed back to the power amplifier via the feedback path. The microprocessor applies phase training signals to the forward path. The microprocessor uses the phase training signals to determine the amount of delay in the linearizer circuit and alters the frequency position of poles and zeros in the linearizer circuit to compensate for the delay. The gain of the linearizer circuit is also altered by the microprocessor depending on the measured delay.
Abstract:
Loop delay in a Cartesian feedback linearised transmitter is computed during a training episode from the settings of the phase shifter 242 required to achieve phase quadrature balance at two frequencies. The pole and zero frequencies of the loop filters 206,209, and the DC loop gain, are then adapted in dependence on the loop delay to maintain stability of the Cartesian loop while minimizing adjacent channel power. If the delay is found to be excessive the transmitter bandwidth may be reduced or the transmitter may be operated in an open loop mode. Improved loop stability allows a Cartesian loop transmitter to be used for broadband signals such as LTE (Long Term Evolution), WiMax, WCDMA and EDGE.
Abstract:
In accordance with the present invention there is those provided a Cartesian loop transmitter having an isolator eliminator circuitry comprising a set of low pass and band pass filters for each of an I- and Q-channels, root mean square detectors and a divider connected to a comparator are received by a microprocessor which controls attenuation setting. There is also provided a method of adjusting an output level of such transmitter. Said method comprises the step of measuring an on-channel signal level and a noise level and then calculating a ratio of said noise to said on-channel signal. If the ratio exceeds a defined threshold an attenuation of the input attenuators is increased.
Abstract:
An integrated circuit includes a linearizer circuit in which excessive delay is compensated. The linearizer circuit includes a power amplifier, forward and feedback paths, and a microprocessor. A signal from the power amplifier is routed by the forward path to be transmitted while a portion of the signal to be transmitted is routed back to the power amplifier via the feedback path. The microprocessor applies phase training signals to the forward path. The microprocessor uses the phase training signals to determine the amount of delay in the linearizer circuit and alters the frequency position of poles and zeros in the linearizer circuit to compensate for the delay. The gain of the linearizer circuit is also altered by the microprocessor depending on the measured delay.