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1.发明申请CODE CONSTRUCTION FOR IRREGULAR SHORTENED LDPC CODES WITH GOOD PERFORMANCE 审中-公开用于具有良好性能的不规则的低密度LDPC码的代码构造
公开(公告)号：WO2005114418A3
公开(公告)日：2006-05-18
申请号：PCT/US2005016410
申请日：2005-05-11
Applicant: MOTOROLA INC , BLANKENSHIP YUFEI , CLASSON BRIAN K
Inventor： BLANKENSHIP YUFEI , CLASSON BRIAN K
CPC classification number: H03M13/618 , H03M13/1148 , H03M13/1165 , H03M13/118 , H03M13/1185
Abstract: A method for interlacing columns of different weights is proposed for a parity-check matrix H (Figure 2) that results in good performing LDPC codes shortened or unshortened. Matrix H comprises a section H 1 and a section H 2 , and wherein H 1 has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlaced between the sub-matrices.
Abstract translation: 对于奇偶校验矩阵H（图2），提出了一种用于交错不同权重的列的方法，该矩阵H导致良好执行的LDPC码被缩短或不启动。 矩阵H包括H 1区和H 2区，并且其中H 1具有多个不同的列权重，并且包括多个 其中至少一个权重的列在子矩阵之间基本上交错的子矩阵。
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Patent Agency Ranking
公开(公告)号：WO2004027616B1
公开(公告)日：2004-05-06
申请号：PCT/US0329073
申请日：2003-09-16
Applicant: MOTOROLA INC
Inventor： BLANKENSHIP YUFEI , CLASSON BRIAN , DESAI VIPUL
CPC classification number: H03M13/1182 , H03M13/09
Abstract: A deterministic structure for controlled distribution of weight-2 columns is proposed that reduces the occurrence of undetected frame errors and significantly enhances the code performance in comparison to a randomly-constructed parity-check matrix.
Abstract translation: 提出了权重2列的受控分布的确定性结构，与随机构建的奇偶校验矩阵相比，减少了未检测到的帧错误的发生并显着增强了代码性能。
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3.发明公开CODE CONSTRUCTION FOR IRREGULAR SHORTENED LDPC CODES WITH GOOD PERFORMANCE 有权CODE建设项目的良好表现不规则缩短的LDPC码
公开(公告)号：EP1747613A4
公开(公告)日：2009-01-21
申请号：EP05747940
申请日：2005-05-11
Applicant: MOTOROLA INC
Inventor： BLANKENSHIP YUFEI , CLASSON BRIAN K
CPC classification number: H03M13/618 , H03M13/1148 , H03M13/1165 , H03M13/118 , H03M13/1185
Abstract: A method for interlacing columns of different weights is proposed for a parity-check matrix H (Figure 2) that results in good performing LDPC codes shortened or unshortened. Matrix H comprises a section H1 and a section H2, and wherein H1 has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlaced between the sub-matrices.
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公开(公告)号：CA2564395A1
公开(公告)日：2005-12-01
申请号：CA2564395
申请日：2005-05-11
Applicant: MOTOROLA INC
Inventor： CLASSON BRIAN K , BLANKENSHIP YUFEI
Abstract: A method for interlacing columns of different weights is proposed for a pari ty- check matrix H (Figure 2) that results in good performing LDPC codes shorten ed or unshortened. Matrix H comprises a section H1 and a section H2, and wherei n H1 has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlac ed between the sub-matrices.
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公开(公告)号：AU2003267242A1
公开(公告)日：2004-04-08
申请号：AU2003267242
申请日：2003-09-16
Applicant: MOTOROLA INC
Inventor： BLANKENSHIP YUFEI , CLASSON BRIAN , DESAI VIPUL
Abstract: The present invention encompasses a method for determining values for parity check bits (p1, . . . , pm) based on a current symbol set (s1, . . . , sk). The method comprises the steps of receiving the current symbol set (s1, . . . , sk) and using a transformation of a matrix to determine the parity check bits. The first N2 columns of the matrix is defined that for column i, 1
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公开(公告)号：CA2564395C
公开(公告)日：2009-07-07
申请号：CA2564395
申请日：2005-05-11
Applicant: MOTOROLA INC
Inventor： BLANKENSHIP YUFEI , CLASSON BRIAN K
Abstract: A method for interlacing columns of different weights is proposed for a pari ty- check matrix H (Figure 2) that results in good performing LDPC codes shorten ed or unshortened. Matrix H comprises a section H1 and a section H2, and wherei n H1 has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlac ed between the sub-matrices.
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