SEMICONDUCTOR PACKAGE AND FORMING METHOD THEREOF

    公开(公告)号:JPH11297729A

    公开(公告)日:1999-10-29

    申请号:JP5446999

    申请日:1999-03-02

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To increase the number of semiconductor dies to be sealed per unit time by arranged the die between the flag part of a first lead frame and the lead part of a second lead frame, forming electrical connections and sealing the die in a molding material, thereby enhancing the rate of operation. SOLUTION: Welded flag frame and clip frame are subjected to reflow soldering process, and solder pools are fused between a semiconductor die 30 and a flag part 7 and between a lead part 19 and a pad position on the die 30. After reflow, the die 30, the flag part 7 and the pair of lead parts 19 are sealed by transfer molding, for example, for forming a semiconductor package. Finally, individual semiconductor packages are separated from the flag frame and the clip frame. Since this method employs only single-pick place step and single- reflow process, high speed package process can be realized.

    Mounting semiconductor components and modules onto coupling frame

    公开(公告)号:DE19903104A1

    公开(公告)日:1999-09-16

    申请号:DE19903104

    申请日:1999-01-27

    Applicant: MOTOROLA INC

    Abstract: The mounting uses a first coupling frame with holding (5) and fin (7) portions, and a second coupling frame of identical configuration. There is at least one semiconductor chip and an encapsulation substance to be located on the fin portion. The first frame is secured to the second one such that the chip is fitted between the fin portion and coupling line. Electric connections are formed between the coupling line and chip as well as between the chip and the fin portion. The whole assembly is then encapsulated. Independent claims are also included for a semiconductor housing and coupling frame.

Patent Agency Ranking