公开(公告)号：WO1981003571A1

公开(公告)日：1981-12-10

申请号：PCT/US1981000607

申请日：1981-05-04

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  DONOGHUE W

IPC: G11C07/02

CPC classification number: G11C7/18 ,  G11C17/126

Abstract: A memory array having improved isolation between the bit sense common lines (22, 23, 26, 27) is provided by using diode connected transistors (40-43). The diode connected transistors (40-43) substantially eliminate any current flow between bit sense common lines (22, 23, 26, 27) when a certain portion of the column select circuitry has not been selected. Since the blocking transistors (40-43) prevent current flow there is no noise generated to be coupled to one of the control lines (28). This results in a memory array which can operate at higher speeds since better differential signals are established to be sensed by the sense amplifier.