公开(公告)号：AU5298801A

公开(公告)日：2001-11-20

申请号：AU5298801

申请日：2001-03-28

Applicant: MOTOROLA INC

Inventor： GONZALES DAVID R ,  BRANSON BRIAN D ,  GUMULJA JIMMY ,  MOYER WILLIAM C

IPC: G06F11/34

Abstract: A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).

公开(公告)号：WO0186447A2

公开(公告)日：2001-11-15

申请号：PCT/US0109872

申请日：2001-03-28

Applicant: MOTOROLA INC

Inventor： GONZALES DAVID R ,  BRANSON BRIAN D ,  GUMULJA JIMMY ,  MOYER WILLIAM C

IPC: G06F11/34

CPC classification number: G06F11/3409 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).

Abstract translation: 性能监视器系统包括核心处理器（115），诸如高速缓存（123）的核心处理器相关设备以及诸如性能逻辑（127）之类的第一逻辑。 核心处理器（115）可操作以执行信息。 核心处理器相关设备提供第一信号（CACHE_PERF），其在核心处理器（115）的操作期间定义核心处理器相关设备（123）的性能。 第一逻辑（127）耦合到核心处理器相关设备（123）并且响应于第二信号（WPT0,1）监视第一信号（CACHE_PERF），其定义与操作相关联的用户可设置属性的匹配 的核心处理器（115）。