MAGNETIC RANDOM ACCESS MEMORY HAVING LAMINATED MEMORY CELLS AND ITS MANUFACTURE

    公开(公告)号:JPH10116490A

    公开(公告)日:1998-05-06

    申请号:JP23178497

    申请日:1997-08-13

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a magnetic random access memory making the density of a memory cell higher and reducing the power consumption. SOLUTION: The magnetic random access memory 10 has plural laminated memory cells on a semiconductor substrate 11 and each memory cell has basically a magnetic material part 12, a word line 13 and a sense line 22. A higher order sense line 22 is electrically coupled to a lower order sense line 12 by ohmic contact through a lead line 23. In order to read out and store a state in the memory cell, by activating the lower and higher order lines 13, 18, all magnetic fields are imparted to the magnetic material part 12. In the magnetic random access memory 10, this laminated memory structure increases a number of the memory cells integrated on the semiconductor substrate 11.

    THREE-DIMENSIONAL MULTILAYER SEMICONDUCTOR CIRCUIT

    公开(公告)号:JP2001044279A

    公开(公告)日:2001-02-16

    申请号:JP19780999

    申请日:1999-07-12

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a three-dimensional semiconductor circuit which is enhanced in circuit density, possessed of an interconnection part reduced in length to an irreducible minimum, enhanced in scale, and made complicated and a method of manufacturing the same. SOLUTION: In a method of manufacturing a three-dimensional semiconductor circuit, a conductive layer possessing a doped polysilicon layer at its upper part is formed, patterned, and annealed for the formation of the first single grain polysilicon terminal 16 of a semiconductor device. An insulated gate contact 30 is set separate from the terminal 16 in the vertically direction, a vertical via is specified, polysilicon is deposited in the via to form a conductive channel 35. The upper part of polysilicon filled in the via is doped for the formation of a second terminal 36 of the semiconductor device, the polysilicon is annealed into a single-grain polysilicon. A second conductive layer 39 is deposited on the second terminal 36 and then patterned, by which the second terminal contact of the semiconductor device is specified.

    LEAN CARRIER DEVICE AND MANUFACTURE

    公开(公告)号:JPH10289998A

    公开(公告)日:1998-10-27

    申请号:JP11282498

    申请日:1998-04-08

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To effectively manufacture a 3-D containment fine structure in a useful device. SOLUTION: A device contains a crystal structure formed of a first material 25 and has a crystallographical facet 26 of certain width and length and a quantum dot 30 which is arranged in a line on the crystallographical facet 26 and is formed of a second material. The line of the quantum dot 30 extends along a lengthwise direction of the crystallographical facet 26 and has approximately one quantum dot width and a length of a plurality of quantum dots. The line of the quantum dot 30 forms a foundation unit for a circuit based on a lean or single electronic device.

    METHOD FOR SELECTING MEMORY CELL IN MAGNETIC RANDOM ACCESS MEMORY DEVICE

    公开(公告)号:JPH10247381A

    公开(公告)日:1998-09-14

    申请号:JP36300097

    申请日:1997-12-12

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a new and improved method for starting a memory cell in a MRAM device that can achieve a high speed operation, especially, a high speed operation in a read-out stage. SOLUTION: The method for selecting a memory cell in a magnetic random access memory(MRAM) is improved. When the state in a memory cell is read out, MRAM adjusts always the output of a compactor to 0V (automatic making 0 stage) before contents of the memory cell are detected. In this method, a sense line 25 is selected once and made automatic 0, memory cells 29, 30 are continuously accessed. Therefore, as this method require no stage in which all read out memory cells are made automatic 0, high speed operation is achieved.

    MEMORY CELL STRUCTURE IN MAGNETIC RANDOM ACCESS MEMORY, AND MANUFACTURING METHOD THEREFOR

    公开(公告)号:JPH10116489A

    公开(公告)日:1998-05-06

    申请号:JP19182997

    申请日:1997-07-01

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure for reducing a word current and a manufacturing method therefor. SOLUTION: The structure of a magnetic random access memory(MRAM) cell having a giant magnetoresistance(GMR) material part 11 wound by a single or many word lines 12 is provided. By superimposing the magnetic field generated by word currents 13, 14 in the GMR material part 11, the magnetic field intensity as a whole is proportionally increased. By passing the same word current through the GMR material part 11 many times, the word magnetic field equivalent to the many times of word magnetic fields generated by a large word current in the conventional MRAM cell is generated.

    7.
    发明专利
    未知

    公开(公告)号:DE69616004T2

    公开(公告)日:2002-06-06

    申请号:DE69616004

    申请日:1996-12-23

    Applicant: MOTOROLA INC

    Abstract: A method of masking surfaces (11) during fabrication of semiconductor devices is disclosed, which includes providing a substrate (10), and in a preferred embodiment a silicon substrate. The surface (11) is hydrogen terminated (12) (or hydrogenated) and a metal mask (15) is positioned on the surface (11, 12) so as to define a growth area (16) and an unmasked portion (17) on the surface (11, 12) Ozone is generated at the surface (11, 12), at least in the unmasked area (17), by exposing the surface (11, 12) to a light (21) having a wavelength approximately 185 nm (an oxygen absorbing peak), so as to grow an oxide film (20) on the unmasked portion (17) of the surface (11, 12). The metal mask (15) is removed and the oxide film (20) then serves as a mask for further operations and can be easily removed in situ by heating.

    8.
    发明专利
    未知

    公开(公告)号:DE69616004D1

    公开(公告)日:2001-11-22

    申请号:DE69616004

    申请日:1996-12-23

    Applicant: MOTOROLA INC

    Abstract: A method of masking surfaces (11) during fabrication of semiconductor devices is disclosed, which includes providing a substrate (10), and in a preferred embodiment a silicon substrate. The surface (11) is hydrogen terminated (12) (or hydrogenated) and a metal mask (15) is positioned on the surface (11, 12) so as to define a growth area (16) and an unmasked portion (17) on the surface (11, 12) Ozone is generated at the surface (11, 12), at least in the unmasked area (17), by exposing the surface (11, 12) to a light (21) having a wavelength approximately 185 nm (an oxygen absorbing peak), so as to grow an oxide film (20) on the unmasked portion (17) of the surface (11, 12). The metal mask (15) is removed and the oxide film (20) then serves as a mask for further operations and can be easily removed in situ by heating.

    Memory cell structure for MRAM
    9.
    发明专利

    公开(公告)号:DE19726077A1

    公开(公告)日:1998-01-08

    申请号:DE19726077

    申请日:1997-06-19

    Applicant: MOTOROLA INC

    Abstract: The cell structure contains a part (10) fabricated from a magnetic material (11) and a conductor (12), with a first leg (12a) on one part side and a second leg (12b) on the other part side. A coupling loop (12c) applies the magnetic field to the magnetic part. Preferably a magnetic flux concentrator is located near the conductor on opposite sides of the magnetic part, to concentrate the field on the magnetic part. A dielectric film may be fitted between the flux concentrator and the magnetic part. The conductor may contain a further part wound round the flux concentrator.

    10.
    发明专利
    未知

    公开(公告)号:DE69523526T2

    公开(公告)日:2002-05-08

    申请号:DE69523526

    申请日:1995-08-17

    Applicant: MOTOROLA INC

    Abstract: A complementary heterojunction semiconductor device (10) has a first resonant interband tunneling transistor (12) coupled to a second resonant interband tunneling transistor (14) through a common output (16). The first transistor (12) has a first gate (18) of a first semiconductor type and a drain (28) coupled to the first gate (18). The first gate (18) is also coupled to the common output (16). The second transistor (14) has a second gate (32) of a second semiconductor type and a source (42) coupled to the second gate (32). The second gate (32) is also coupled to the common output (16). The valence band (60,80,82) of the first semiconductor type has an energy level greater than the conduction band (62,64,84) of the second semiconductor type.

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