公开(公告)号：JPH11234125A

公开(公告)日：1999-08-27

申请号：JP21197598

申请日：1998-07-10

Applicant: MOTOROLA INC

Inventor： HARDESTY JEFFREY R ,  HALL GEOFFREY ,  MCCOLLOUGH KELVIN

IPC: G06F1/04 ,  G06F1/08 ,  H03K21/00 ,  H03L7/08 ,  H03L7/095 ,  H03L7/10 ,  H03L7/107 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To provide a PLL clock generation system capable of eliminating faults due to overshoot without delaying a processor and reducing the time of a full power mode. SOLUTION: A PLL 310 generates PLL clock output to a frequency divider 330 for frequency dividing a PLL clock. The PLL 310 outputs a frequency lock signal corresponding to the acquisition of a desired output frequency and it starts a counter 320 and enables the execution of a CPU 350 clocked by a system clock. Thus, the CPU 350 performs execution during phase lock at a frequency-divided frequency without the danger of the fault by frequency overshooting. A phase lock signal outputted by the counter 320 is logically connected with signal output from the CPU 350 for requesting a maximum frequency operation. The frequency divider 330 is selected by the connected signal and the CPU 350 performs the execution at the maximum frequency when the PLL 310 is safely phase locked.

公开(公告)号：DE69817713D1

公开(公告)日：2003-10-09

申请号：DE69817713

申请日：1998-07-13

Applicant: MOTOROLA INC

Inventor： HARDESTY JEFFREY R ,  HALL GEOFFREY ,  MCCOLLOUGH KELVIN

IPC: G06F1/04 ,  G06F1/08 ,  H03K21/00 ,  H03L7/08 ,  H03L7/095 ,  H03L7/10 ,  H03L7/107 ,  H03L7/18 ,  H03L7/06

Abstract: A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

公开(公告)号：DE69817713T2

公开(公告)日：2004-04-08

申请号：DE69817713

申请日：1998-07-13

Applicant: MOTOROLA INC

Inventor： HARDESTY JEFFREY R ,  HALL GEOFFREY ,  MCCOLLOUGH KELVIN

IPC: G06F1/04 ,  G06F1/08 ,  H03K21/00 ,  H03L7/08 ,  H03L7/095 ,  H03L7/10 ,  H03L7/107 ,  H03L7/18 ,  H03L7/06

Abstract: A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.