公开(公告)号：JPH11175391A

公开(公告)日：1999-07-02

申请号：JP27433698

申请日：1998-09-10

Applicant: MOTOROLA INC

Inventor： HANSEN JOHN PHILLIP ,  METZGER ERIK

IPC: G11C16/06 ,  G06F12/00 ,  G06F13/42 ,  G11C16/02 ,  G11C16/10 ,  G11C16/26

Abstract: PROBLEM TO BE SOLVED: To reduce readout delay without increasing the system cost, weight, power consumption, and complexity of a data processing system by automatically expanding and restarting writing/erasing operation of a bank of a flash memory when the same bank needs to be read. SOLUTION: The flash memory 12 has banks of memory cells. When a request to read the flash memory 12 at the same bank with a memory cell where writing/erasing operation is performed, the writing/erasing operation is extended while the reading operation is carried out. A wait signal RDY/ WAIT* is asserted by the flash memory 12, and consequently the extension of the writing/erasing operation is shown to a processor 10. After read data are prepared, the wait signal RDY/WAIT* is negated. When more than one reading operation is requested, following reading operations are all performed before the writing/erasing operation is restarted.

公开(公告)号：JPH11175399A

公开(公告)日：1999-07-02

申请号：JP27432798

申请日：1998-09-10

Applicant: MOTOROLA INC

Inventor： HANSEN JOHN PHILLIP ,  METZGER ERIK

IPC: G11C16/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06

Abstract: PROBLEM TO BE SOLVED: To discriminate a command mode read and a memory mode read of a flash memory system by allowing a read command to mean reception following a command read indication in a memory cycle or a memory read of bits and transfer to a processor without the command read indication. SOLUTION: When a writable signal is asserted (S60), a command mode is entered (S64). When a command is equal to a command end mode command (S66), the command mode ends (S72). When the command is not equal (S66), on the other hand, a command received from a processor is processed (S74). When the writable signal is not asserted (S60) and the command read indication is not received in a memory cycle (S62), a read is indicated and transfer to the processor is performed (S68). When the indication is received (S62), the contents of a register are transferred to the processor (S70).