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公开(公告)号：JP2000151396A
公开(公告)日：2000-05-30
申请号：JP31452399
申请日：1999-11-05
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER W , GONZALEZ DAVID M
Abstract: PROBLEM TO BE SOLVED: To provide a phase detector for a PLL (phase-locked loop), minimizing a false lock between a frequency-division reference frequency signal and the signal from a loop frequency divider. SOLUTION: A PLL 212 is equipped with a phase detector 202 and a charge pump 210 or 212. The phase detector 202 is equipped with flip-flops 302 and 310 and an AND gate which forms a reset circuit 306. The charge pump 210 is equipped with an up-current source 308 and a down-current source 310 which supply constant currents. The down-current source 310 varies responding to the output signal 207 generated by the flip-flop 310. The constant current of the up current source 308 is reduced to less than half of the current of the down-current source 310 and biases the charge pump 210 in negative direction to minimize the false lock between the phases of the reference frequency-division signal 206 and the signal 209 from the loop frequency divider.
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公开(公告)号：FI108381B
公开(公告)日：2002-01-15
申请号：FI921959
申请日：1992-04-30
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER W , RABE DUANE C
Abstract: The latched accumulator fractional-N synthesiser has reduced residual error for use in digital radio transceivers. The divisor of the frequency divider (103) of the synthesiser is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched so that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, so that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).
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公开(公告)号：DE19707990C2
公开(公告)日：1999-04-15
申请号：DE19707990
申请日：1997-02-27
Applicant: MOTOROLA INC
Inventor： ABDI BEHROOZ L , GONZALEZ DAVID M , HIETALA ALEXANDER W
Abstract: A communication device (100) employs a local oscillator (104) having an improved charge pump circuit (122). The charge pump circuit (122) has current mirrors (204, 208) in which a first transistor (224, 270) is biased to provide a substantially constant current. A resistor (226, 272) selectively conducts a reference current to bias a mirror transistor (228, 274). The current mirror (204, 208) provides improved dynamic performance thereby reducing global phase error of the communication device (100).
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公开(公告)号：CA2089480C
公开(公告)日：1998-12-08
申请号：CA2089480
申请日：1992-06-08
Applicant: MOTOROLA INC
Inventor： BLACK GREGORY R , HIETALA ALEXANDER W , AGAHI-KESHEH DARIOUSH
Abstract: A voltage controlled oscillator and buffer amplifier circuit (211) is disclosed. The circuit is in a stacked configuration, whereby, the current from the power supply (361) is used by the buffer amplifier circuit and reused by the VCO circuit. The VCO circuit includes two transistors (333, 325). The transistors are set-up in a mirrored configuration, so that one of the transistors (325) controls the bias current in the other transistor (333). Both of the transistors are integrated into a semiconductor circuit die (365), thus, matching the thermal characteristics of the transistors (333, 325) and improving control of the bias current. The die (365) is bonded to a ceramic substrate (601). The substrate (601) has connectivity paths for connecting components in the circuit die to components external to the circuit die. Some of the connectivity paths are made of a material and length to form passive circuit elements.
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公开(公告)号：FR2715012B1
公开(公告)日：1998-06-12
申请号：FR9412603
申请日：1994-10-21
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER W
Abstract: A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).
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Patent Agency Ranking
公开(公告)号：FR2734910B1
公开(公告)日：1998-03-27
申请号：FR9606211
申请日：1996-05-20
Applicant: MOTOROLA INC
Inventor： JANSSEN JOHN J , HIETALA ALEXANDER W
IPC: H04B1/40 , G01R31/28 , G01R31/36 , G01R31/40 , H02J7/00 , H04B1/38 , H04B7/26 , H04M19/08 , H04Q7/20
Abstract: A portable radio communication device (303) includes power control circuitry (315) for monitoring the voltage level incoming from a battery (317), and provides power to the rest of the radio communication device (303). The power control circuitry (315) includes a boost regulator (407) that is used to generate an internal reference signal for use throughout the radio communication device including an analog to digital converter (ADC) for digitizing the battery voltage for use by the power control circuitry (315). The power control circuitry (315) compares the digitized battery voltage to thresholds to control power to the remainder of the radio communication device (303). Additionally, a secondary comparator (413) is provided to prevent damage to the battery and radio communication device circuitry. The secondary comparator uses multiple undervoltage thresholds depending upon the power state of the radio communication device (303).
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公开(公告)号：CA2150818C
公开(公告)日：1997-11-18
申请号：CA2150818
申请日：1994-09-12
Applicant: MOTOROLA INC
Inventor： HIETALA ALEXANDER W , RABE DUANE C
Abstract: The preferred embodiment of the present invention encompasses an automatic frequency control system implemented in a radiotelephone (101). The radiotelephone (101) includes a frequency synthesizer. The frequency synthesizer uses a division ratio varied with time by a multi accumulator fractional N division system (140) such that the effective division radio may be varied by non-integer steps. The division radio is programmed to realize the desired channel frequency, the desired channel frequency modulation waveform, and any automatic frequency correction offset. An accurate clock is provided to the control (104) and the user interface (105) sections of the radiotelephone (101) using a second multiple accumulation fractional N division system (139). This second fractional N division system (139) is programmed based on the automatic frequency control programming of the first fractional N division system (140). This lower frequency may then be multiplied in a phase locked loop to provide an accurate reference at a second reference frequency.
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公开(公告)号：DE19707990A1
公开(公告)日：1997-11-13
申请号：DE19707990
申请日：1997-02-27
Applicant: MOTOROLA INC
Inventor： ABDI BEHROOZ L , GONZALEZ DAVID M , HIETALA ALEXANDER W
Abstract: A communication device (100) employs a local oscillator (104) having an improved charge pump circuit (122). The charge pump circuit (122) has current mirrors (204, 208) in which a first transistor (224, 270) is biased to provide a substantially constant current. A resistor (226, 272) selectively conducts a reference current to bias a mirror transistor (228, 274). The current mirror (204, 208) provides improved dynamic performance thereby reducing global phase error of the communication device (100).
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公开(公告)号：FR2745449A1
公开(公告)日：1997-08-29
申请号：FR9701940
申请日：1997-02-19
Applicant: MOTOROLA INC
Inventor： BLACK GREGORY R , HIETALA ALEXANDER W , BURNS MARK ROBERT
Abstract: A communication device (104) comprises a receiver circuit (108) receiving a modulated receive signal. A reference oscillator (132) generates a first clock signal at a first frequency, the first clock signal having harmonics. Circuitry (130) coupled to the reference oscillator and to the receiver responds to the first clock signal to produce a signal used by the receiver to reduce the frequency of the modulating signal. A frequency spreading circuit (134) is also coupled to the reference oscillator to modulate the first clock signal with a frequency spreading signal to produce a modulated clock signal including modulated harmonic frequency components. The frequency spreading circuit selectively combines the frequency spreading signal and the first clock signal. A control circuit (114) controls the frequency spreading circuit to modulate first clock signal with the frequency spreading signal when the selected received signal includes a harmonic of the first clock signal.
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公开(公告)号：HU213441B
公开(公告)日：1997-06-30
申请号：HU9300277
申请日：1992-05-08
Applicant: MOTOROLA INC
Inventor： BLACK GREGORY R , HIETALA ALEXANDER W
Abstract: A power amplifier controller for detecting saturation of the power amplifier (203) and corrects the automatic output control voltage (231) to avoid any further saturation. A detector (211) detects the power of the radio frequency (RF) output signal (211) and generates a signal (229) correlated to the detected power. Comparator (217) compares changes in that signal (229) to changes in the voltage of the AOC signal (231). The comparator (217) generates a signal (233) correlated to saturation of the power amplifier (203) for a DSP (223). The DSP (223) checks the status of this signal (233). Upon detecting saturation, an algorithm contained within the DSP methodically reduces the voltage of the AOC signal (231) until there is a change in the power of the RF output signal (211).
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