公开(公告)号：DE3176487D1

公开(公告)日：1987-11-19

申请号：DE3176487

申请日：1981-08-21

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER LEE ,  JACOBSON JAMES EVERETTE

IPC: G06F1/00 ,  G06F1/24 ,  G06F1/32 ,  G06F9/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/30 ,  H04Q7/14

Abstract: A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.

公开(公告)号：BR8108826A

公开(公告)日：1982-08-24

申请号：BR8108826

申请日：1981-08-31

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER LEE ,  JACOBSON JAMES EVERETTE

IPC: G05F1/56 ,  G05F3/20 ,  H02M3/155 ,  H02M3/156 ,  H02M3/335

Abstract: A DC/DC converter operates at peak efficiency in either of two output current level states in response to the power demands of an associated electronic device, thereby reducing wasted current to a minimum. The converter is designed to operate from a one-cell battery, and is particularly suited to an integrated circuit implementation.