Abstract:
Apparatus, computer program, and method for producing filter coefficients for an equalizer, the method includes the steps of: estimating a response (810) of a communication channel to a signaling pulse; estimating an autocorrelation (820) of noise and interference of the communication channel; computing an array (830) based on the estimation of the response of the communication channel to the signaling pulse and the estimation of the autocorrelation of the noise and interference of the communication channel; designating (840) at least one pivot position in the array; recursively performing the steps of: transforming the array (850) by a sequence of operations; storing (860) at least one element of the at least one pivot position; shifting (870) the at least one element of the at least one pivot position, thereby providing a shifted transformed array; determining (890) whether the shifted transformed array contains at least one non-zero element; and calculating (880) the filter coefficients based on the stored at least one element and the estimation of the response of the communication channel.
Abstract:
A first group of bits (100, 102, 106), e.g., header symbols/bits, are interleaved to form a first group of interleaved bits. A second group of bits (104), e.g., data symbols/bits, are interleaved to form a second group of interleaved bits. The first and second groups of interleaved bits are mapped to an information burst (114). The first and second groups of interleaved bits may be mapped to the information burst relative to a group of known symbols (116) forming a training sequence. A disadvantaged bit location, i.e., a bit location within the mapping having a relative high probability of incurring a bit error, is identified and an advantaged bit location, i.e., a bit location within the mapping having a relatively low probability of incurring a bit error, is identified. A first group bit from the first group of interleaved bits mapped to the disadvantaged bit location is remapped to the advantaged bit location while a second group bit from the second group of interleaved bits mapped to the advantaged bit location is remapped to the disadvantaged bit location.
Abstract:
A first group of bits (100, 102, 106) e.g., header symbols/bits, are interleaved to form a first group of interleaved bits. A second group of bits (104), e.g., data symbols/bits, are interleaved to form a second group of interleaved bits. The first and second groups of interleaved bits are mapped to an information burst (114). The first and second groups of interleaved bits may be mapped to the information burst relative to a group of known symbols (116) forming a training sequence. A disadvantaged bit location, i.e., a bit location within the mapping having a relative high probability of incurring a bit error, is identified and an advantaged bit location, i.e., a bit location within the mapping having a relatively low probability of incurring a bit error, is identified. A first group bit from the first group of interleaved bits mapped to the disadvantaged bit location is remapped to the advantaged bit location while a second group bit from the second group of interleaved bits mapped to the advantaged bit location is remapped to the disadvantaged bit location.
Abstract:
A first group of bits (100, 102, 106) e.g., header symbols/bits, are interleaved to form a first group of interleaved bits. A second group of bits (104), e.g., data symbols/bits, are interleaved to form a second group of interleaved bits. The first and second groups of interleaved bits are mapped to an information burst (114). The first and second groups of interleaved bits may be mapped to the information burst relative to a group of known symbols (116) forming a training sequence. A disadvantaged bit location, i.e., a bit location within the mapping having a relative high probability of incurring a bit error, is identified and an advantaged bit location, i.e., a bit location within the mapping having a relatively low probability of incurring a bit error, is identified. A first group bit from the first group of interleaved bits mapped to the disadvantaged bit location is remapped to the advantaged bit location while a second group bit from the second group of interleaved bits mapped to the advantaged bit location is remapped to the disadvantaged bit location.