公开(公告)号：IT8248321D0

公开(公告)日：1982-04-30

申请号：IT4832182

申请日：1982-04-30

Applicant: MOTOROLA INC

Inventor： ASPIN CARLTON H ,  LO WEI JEN

IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L

公开(公告)号：WO1982003948A1

公开(公告)日：1982-11-11

申请号：PCT/US1982000472

申请日：1982-04-15

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  ASPIN CARLTON H ,  LO WEI JEN

IPC: H01L29/04

CPC classification number: H01L29/66575 ,  H01L21/0272 ,  H01L23/485 ,  H01L23/53257 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Lower contact and interconnect metallization series resistance on semiconductor devices is achieved while avoiding the material and process incompatibility problems of the prior art by utilizing a composite metallization (42, 44, 49) structure employing two superposed intermetallic layers (44, 49) of different properties. The first intermetallic (44) is chosen for high conductivity and compatibility with the device interfaces. The second intermetallic (49) functions as a conductive protective "cap" and is chosen for conductivity and compatibility with subsequent process steps. The two intermetallics (44, 49) must also be compatible. For silicon devices the preferred first and second intermetallics are respectively, silicon rich titanium silicide and titanium nitride, but other materials are also useful. Polycrystalline silicon (42) is desirable for a base layer under the first intermetallic (44) in certain device structures such as MOS gates. The composite metallization is prepared by a lift-off technique.

Abstract translation: 通过利用具有不同性质的两个重叠的金属间化合物层（44,49）的复合金属化（42,44,49）结构，避免了现有技术的材料和工艺不兼容性问题，实现了半导体器件上的低接触和互连金属化串联电阻， 。 选择第一金属间化合物（44）用于高电导率和与器件界面的兼容性。 第二金属间化合物（49）用作导电保护“帽”，并被选择用于导电性和与后续工艺步骤的兼容性。 两个金属间化合物（44,49）也必须兼容。 对于硅器件，优选的第一和第二金属间化合物分别是富硅钛硅化物和氮化钛，但是其它材料也是有用的。 在诸如MOS栅极的某些器件结构中，多晶硅（42）对于第一金属间化合物（44）下的基底层是理想的。 通过剥离技术制备复合金属化。

公开(公告)号：DE3268922D1

公开(公告)日：1986-03-20

申请号：DE3268922

申请日：1982-04-15

Applicant: MOTOROLA INC

Inventor： ASPIN CARLTON H ,  LO WEI JEN

IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/04 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

公开(公告)号：EP0077813A4

公开(公告)日：1984-02-09

申请号：EP82901672

申请日：1982-04-15

Applicant: MOTOROLA INC

Inventor： ASPIN CARLTON H ,  LO WEI JEN

IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/04 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC classification number: H01L29/66575 ,  H01L21/0272 ,  H01L23/485 ,  H01L23/53257 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Lower contact and interconnect metallization series resistance on semiconductor devices is achieved while avoiding the material and process incompatibility problems of the prior art by utilizing a composite metallization (42, 44, 49) structure employing two superposed intermetallic layers (44, 49) of different properties. The first intermetallic (44) is chosen for high conductivity and compatibility with the device interfaces. The second intermetallic (49) functions as a conductive protective "cap" and is chosen for conductivity and compatibility with subsequent process steps. The two intermetallics (44, 49) must also be compatible. For silicon devices the preferred first and second intermetallics are respectively, silicon rich titanium silicide and titanium nitride, but other materials are also useful. Polycrystalline silicon (42) is desirable for a base layer under the first intermetallic (44) in certain device structures such as MOS gates. The composite metallization is prepared by a lift-off technique.