公开(公告)号：WO1981000494A1

公开(公告)日：1981-02-19

申请号：PCT/US1980000959

申请日：1980-07-21

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  MCALLISTER D ,  PFIESTER J

IPC: G11C08/00

CPC classification number: G11C8/10 ,  G11C11/4087 ,  H03K19/09441 ,  H03K19/096

Abstract: A decoder circuit suitable for integrated circuit implementation using IGFET processing which may be implemented in a highly dense structure. The decoder output lines (54', 56') are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices (38, 40) are used in place of a single IGFET device (30) in order to reduce the chip area required to implement the decoder structure.