公开(公告)号：FR2770314B1

公开(公告)日：2000-07-07

申请号：FR9812425

申请日：1998-10-05

Applicant: MOTOROLA INC

Inventor： SILK S DAVID ,  PORRETT EDWARD C

IPC: H04L29/06 ,  G06F3/00 ,  H04L29/12 ,  H04B10/00

Abstract: A controller circuit (107) between a transceiver (104) and an RS232communication port (103) provides wireless communication to a remote unit and includes a transmitting and receiving mode indicator (503), a first delay circuit (506) for delaying a packet of data (501) before being transmitted, a timer (502) counting a period of time during which delaying termination of transmitting mode following a last data bit of the packet of data (501). Further, a receive signal detector (504) produces a carrier detect signal (521) and its delayed version (525) through a second delay (522) when a data packet (520) is received from the transceiver (104), first and second AND gates (523, 528) and a third delay circuit (526) receive signals (525and 520) to produce a reformatted received data packet (529) compatible to the RS232format for input to the RS232communication port (103).

公开(公告)号：FR2770314A1

公开(公告)日：1999-04-30

申请号：FR9812425

申请日：1998-10-05

Applicant: MOTOROLA INC

Inventor： SILK S DAVID ,  PORRETT EDWARD C

IPC: H04L29/06 ,  G06F3/00 ,  H04L29/12 ,  H04B10/00

Abstract: A signal (503) passes directly, and also through an inverter (505), to a logic interface (504), to control the receiving and transmitting modes of a transceiver (104). A controller circuit (107) provides wireless communications to a transmitting block (108), transmitting leading logic zero data bits before the transmitted data packet arrives at the logic interface. The delay in a delay stage (506) equals the period of the leading zeros and a computed reformatted data packet is input to the RS232 port from another delay circuit (526). An Independent claim is included for a controller circuit between a transceiver and RS232 communication port.