Calibration device for a phase locked loop synsthesiser

    公开(公告)号:GB2408398A

    公开(公告)日:2005-05-25

    申请号:GB0326861

    申请日:2003-11-18

    Applicant: MOTOROLA INC

    Abstract: A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration phase locked loop synthesizer device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path.

    A predistorter for a polar transmitter, using look-up tables and interpolation, and possessing a simple training procedure.

    公开(公告)号:GB2407929A

    公开(公告)日:2005-05-11

    申请号:GB0325852

    申请日:2003-11-05

    Abstract: An amplitude predistorter for an EDGE polar RF transmitter comprises a look-up table 205 containing a small set of input-output values defining a piecewise linear model of the amplitude response of the amplifier (105, figure 1). The two input-output value pairs defining the segment in which the input amplitude lies are fed from the LUT 205 to a linear interpolator 204. A phase correction look-up table may be provided also (figure 4). The precorrection unit 201 provides scaling and offset to match the input signal range to the available amplifier output range. The contents of the look-up tables may be determined relatively promptly and without iteration during a training mode, using a low-bandwidth Cartesian receiver (106, figure 1). The LUT 205 may contain a bitmap denoting whether each segment end point is above or below the input to the LUT. The priority encoder 203 operates on the bitmap output to select a segment.

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