公开(公告)号：WO1982000742A1

公开(公告)日：1982-03-04

申请号：PCT/US1981000885

申请日：1981-06-29

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  JASPER S ,  PREDINA J

IPC: H04L07/02

CPC classification number: H04L7/033 ,  H04L7/027

Abstract: As shown in Fig. 4 a phase corrected clock signal recovery circuit (150) for multilevel digital signals includes a transition marker generator (200) for generating a narrow width pulse each time a received multilevel digital signal crosses one of the threshold levels between the adjacent logic levels of multilevel signal. Picket fence-like pulse trains are thus formed, the pulses (transition markers) of which correspond to the threshold crossings of the received digital signal. The pulse trains are interspersed with spaces or eye intervals which correspond to the absence of any threshold crossings. Each eye interval additionally corresponds to the time during which each respective bit of digital signal information is transmitted. The rate of occurrence of the pulse trains is substantially equal to the clock frequency of the received digital signal. A phase error detection circuit (400) is operatively coupled to the output of the transition marker generator (200) and to an electronically tune bandpass filter (300) capable of adjusting the phase of the pulse trains. More specifically, the phase error detection circuit (400) includes an up/down counter (410, 411) and adjusts the phase of the clock signal recovered from the pulse trains such that the number of transition markers generated during the high portion of the clock signal equals the number of transition markers generated during the low portion of the clock signal. Thus, selected transitory edges of the pulses of the recovered clock signal are centered at the middles of the respective eye intervals, that is, at the points in time when each respective bit of multilevel digital signal information occurs. This phase corrected recovered clock signal is conveniently applied to appropriate sampling circuitry to enable sampling of the multilevel digital signal at optimum times, that is, at the center of the eye intervals.

Abstract translation: 如图所示。 如图4所示，用于多电平数字信号的相位校正时钟信号恢复电路（150）包括用于每当接收的多电平数字信号跨越多电平信号的相邻逻辑电平之间的阈值电平之一时产生窄宽度脉冲的转换标记发生器（200） 。 因此，形成了栅栏状的脉冲序列，其脉冲（转换标记）对应于接收的数字信号的阈值交叉。 脉冲串散布有空格或眼睛间隔，对应于没有任何阈值交叉。 每个眼睛间隔另外对应于发送数字信号信息的每个相应位的时间。 脉冲串的发生率基本上等于接收的数字信号的时钟频率。 相位误差检测电路（400）可操作地耦合到转换标记产生器（200）的输出端和能够调节脉冲串相位的电子调谐带通滤波器（300）。 更具体地，相位误差检测电路（400）包括一个向上/向下计数器（410,411），并且调整从脉冲序列恢复的时钟信号的相位，使得在时钟的高部分期间产生的转换标记的数量 信号等于在时钟信号的低部分期间产生的转换标记的数量。 因此，恢复的时钟信号的脉冲的选定的临时边缘以相应的眼睛间隔的中心为中心，即在出现每个相应位的多电平数字信号信息的时间点。 该相位校正的恢复时钟信号方便地应用于适当的采样电路，以便能够在最佳时间，即在眼睛间隔的中心对多电平数字信号进行采样。