Abstract:
A high speed comparator comprising an operational amplifier and two inverter portions is provided. The output voltage of the operational amplifier biases a control transistor coupled to the first inverter portion which is coupled to the operational amplifier in a closed loop. A stable reference voltage is coupled to an input of the operational amplifier and forces the switch point of the first inverter to be at the reference voltage. If the second inverter portion comprises transistors having the gate dimensions thereof sized the same as the transistors of the first inverter portion, the switch point of the second inverter is also at the reference voltage. The switch point of the fast comparator has thereby been isolated from process and temperature variations.
Abstract:
An input buffer circuit having a single input for receiving input voltages characterized by having varying voltage swings is provided. First and second inverter circuits having differing switchpoint voltages are coupled to a level shifting position. The level shifting portion varies the level of swing of the input voltage and buffers the input voltage. In one form, voltage coupling circuitry is interposed between the level shifting portion and a latching portion which provides the input voltage as an output signal at a predetermined voltage level. In another form, voltage coupling circuitry controlled by control circuitry couples the output of the level shifting portion to an output in response to the input voltage.
Abstract:
A high speed comparator comprising an operational amplifier and two inverter portions is provided. The output voltage of the operational amplifier biases a control transistor coupled to the first inverter portion which is coupled to the operational amplifier in a closed loop. A stable reference voltage is coupled to an input of the operational amplifier and forces the switch point of the first inverter to be at the reference voltage. If the second inverter portion comprises transistors having the gate dimensions thereof sized the same as the transistors of the first inverter portion, the switch point of the second inverter is also at the reference voltage. The switch point of the fast comparator has thereby been isolated from process and temperature variations.
Abstract:
A CURRENT SOURCE CIRCUIT HAVING REDUCED ERROR A current source circuit which provides an output bias current having reduced error is disclosed. The current source has reference voltage and reference current portions coupled together for providing a reference current to an amplifier portion. A buffer portion is coupled to the amplifier portion and to a bias current portion for substantially increasing the output impedance of the amplifier portion thereby decreasing the effect of power supply variation on the output bias current.
Abstract:
A HIGH SPEED CMOS COMPARATOR CIRCUIT A high speed comparator comprising an operational amplifier and two inverter portions is provided. The output voltage of the operational amplifier biases a control transistor coupled to the first inverter portion which is coupled to the operational amplifier in a closed loop. A stable reference voltage is coupled to an input of the operational amplifier and forces the switch point of the first inverter to be at the reference voltage. If the second inverter portion comprises transistors having the gate dimensions thereof sized the same as the transistors of the first inverter portion, the switch point of the second inverter is also at the reference voltage. The switch point of the fast comparator has thereby been isolated from process and temperature variations.
Abstract:
INPUT BUFFER CIRCUIT FOR RECEIVING MULTIPLE LEVEL INPUT VOLTAGES An input buffer circuit (10) having a single input for receiving input voltages (VIN) characterized by having varying voltage swings is provided. First (12 and 15) and second (16 and 18) inverter circuits having differing switchpoint voltages are coupled to a level shifting portion (13, 17). The level shifting portion varies the level of swing of the input voltage (VIN) and buffers the input voltage (VIN). In one form, voltage coupling circuitry (22, 23) is interposed between the level shifting portion and a latching portion (25, 26) which provides the input voltage (VIN) as an output signal at a predetermined voltage level. In another form, voltage coupling circuitry (48, 53) controlled by control circuitry (49, 50, 57) couples the output of the level shifting portion (43, 44) to an output in response to the input voltage (VIN).
Abstract:
A high speed comparator comprising an operational amplifier and two inverter portions is provided. The output voltage of the operational amplifier biases a control transistor coupled to the first inverter portion which is coupled to the operational amplifier in a closed loop. A stable reference voltage is coupled to an input of the operational amplifier and forces the switch point of the first inverter to be at the reference voltage. If the second inverter portion comprises transistors having the gate dimensions thereof sized the same as the transistors of the first inverter portion, the switch point of the second inverter is also at the reference voltage. The switch point of the fast comparator has thereby been isolated from process and temperature variations.