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    1.
    发明专利
    未知

    公开(公告)号：IT1142739B

    公开(公告)日：1986-10-15

    申请号：IT4923681

    申请日：1981-09-04

    Applicant: MOTOROLA INC

    Inventor： SMITH PHILIP SOMERSET

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/575 ,  G06F

    Abstract: A CMOS static ALU is capable of selecting one operand from a plurality of inputs and can perform various arithmetic and logic operations in addition to shift left and shift right operations. The ALU uses exclusive OR gates having a minimum number of transistors. In addition, more N-channel transistors are used than P-channel transistors which results in overall smaller size and faster operation. In addition, the ALU has a RAM cell for use as a temporary storage means which is capable of driving the ALU data bus.

    2.
    发明专利
    未知

    公开(公告)号：IT8149236D0

    公开(公告)日：1981-09-04

    申请号：IT4923681

    申请日：1981-09-04

    Applicant: MOTOROLA INC

    Inventor： SMITH PHILIP SOMERSET

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/575 ,  G06F

    Abstract: A CMOS static ALU is capable of selecting one operand from a plurality of inputs and can perform various arithmetic and logic operations in addition to shift left and shift right operations. The ALU uses exclusive OR gates having a minimum number of transistors. In addition, more N-channel transistors are used than P-channel transistors which results in overall smaller size and faster operation. In addition, the ALU has a RAM cell for use as a temporary storage means which is capable of driving the ALU data bus.

    CMOS MICROPROCESSOR ARCHITECTURE
    4.
    发明专利
    CMOS MICROPROCESSOR ARCHITECTURE 未知

    公开(公告)号：DE3071812D1

    公开(公告)日：1986-12-04

    申请号：DE3071812

    申请日：1980-08-07

    Applicant: MOTOROLA INC

    Inventor： RAGHUNATHAN KUPPUSWAMY ,  SMITH PHILIP SOMERSET

    IPC: G06F9/30 ,  G06F9/32 ,  G06F15/02 ,  G06F15/78 ,  G06F9/06

    Abstract: A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register. An ALU has a first and a second input, which because of the bus structure used, can both receive data simultaneously.

    5.
    发明专利
    未知

    公开(公告)号：DE3071219D1

    公开(公告)日：1985-12-12

    申请号：DE3071219

    申请日：1980-08-07

    Applicant: MOTOROLA INC

    Inventor： SMITH PHILIP SOMERSET

    IPC: G06F7/50 ,  G06F7/505 ,  G06F7/508 ,  G06F9/32 ,  H03K23/00

    Abstract: An increment/decrement circuit is provided which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/decrement circuit and also uses a reduced number of transistors. The increment/decrement circuit has a carry/borrow generator and has an increment/decrement output portion. The carry/borrow generator uses only three transistors plus an inverter and two coupling transistors. The increment/decrement output portion uses only six transistors.

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