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    OPTICAL WAVEGUIDE TRENCHES IN COMPOSITE INTEGRATED CIRCUITS
    3.
    发明申请
    OPTICAL WAVEGUIDE TRENCHES IN COMPOSITE INTEGRATED CIRCUITS 审中-公开
    复合集成电路中的光波导路径

    公开(公告)号：WO03009024A3

    公开(公告)日：2003-06-05

    申请号：PCT/US0214363

    申请日：2002-05-06

    Applicant: MOTOROLA INC

    Inventor： TALIN ALBERT A ,  BARENBURG FOLEY BARBARA

    IPC: G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02B6/43

    CPC classification number: G02B6/132 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/1215

    Abstract: High quality epitaxial layers of compound semiconductor materials (26) can be grown overlying large silicon wafers(22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between theaccommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Trenches (1038,1042,1046) in composite integrated circuits (1034) are provided that may be used for electrical isolation and strain relief. The trenches (1050,1052,1054) may also be implemented as optical waveguides to carry optical signals on- or off-chip.

    Abstract translation: 通过首先在硅晶片上生长适应缓冲层（24），可以在大硅晶片（22）上生长高质量的化合物半导体材料外延层（26）。 适应缓冲层是由硅氧化物的无定形界面层（28）与硅晶片隔开的单晶氧化物层。 非晶界面层消散应变并允许高质量单晶氧化物容纳缓冲层的生长。 适应缓冲层与下面的硅晶片和上面的单晶化合物半导体层晶格匹配。 缓冲层和底层硅衬底之间的任何晶格失配由无定形界面层处理。 提供复合集成电路（1034）中的沟槽（1038,1042,1046），其可用于电隔离和应变消除。 沟槽（1050,1052,1054）也可以被实现为用于在芯片上或芯片外传送光信号的光波导。

    A NANO-SUPPORTED CATALYST FOR NANOTUBE GROWTH
    4.
    发明申请
    A NANO-SUPPORTED CATALYST FOR NANOTUBE GROWTH 审中-公开
    纳米支持的纳米生长催化剂

    公开(公告)号：WO03024594A3

    公开(公告)日：2003-08-07

    申请号：PCT/US0225373

    申请日：2002-08-09

    Applicant: MOTOROLA INC

    Inventor： TALIN ALBERT A ,  COLL BERNARD F ,  DEAN KENNETH A ,  STAINER MATTHEW

    IPC: B01J21/04 ,  B01J21/10 ,  B01J23/38 ,  B01J23/58 ,  B01J23/745 ,  B01J23/78 ,  B01J35/00 ,  B01J37/34 ,  C25D7/00 ,  D01F9/127 ,  B01J35/06 ,  B01J35/10

    CPC classification number: B82Y15/00 ,  B01J21/04 ,  B01J21/10 ,  B01J23/38 ,  B01J23/58 ,  B01J23/745 ,  B01J23/78 ,  B01J35/0013 ,  B01J37/348 ,  B82Y10/00 ,  C25D7/00 ,  H01J2201/30469 ,  Y10S977/835 ,  Y10S977/843 ,  Y10S977/847

    Abstract: Methods of forming a nano-supported catalyst on a substrate and at least one carbon nanotube on the substrate are comprised of configuring a substrate with an electrode (102), immersing the substrate with the electrode into a solvent containing a first metal salt and a second metal salt (104) and applying a bias voltage to the electrode such that a nano-supported catalyst is at least partly formed with the first metal salt and the second metal salt on the substrate at the electrode (106). In addition, the method of forming at least one carbon nanotube is comprised of conducting a chemical reaction process such as catalytic decomposition, pyrolysis, chemical vapor deposition, or hot filament chemical vapor deposition o grow at least one nanotube on the surface of the nano-supported catalyst (108).

    Abstract translation: 在基板上形成纳米载体的催化剂和在基板上形成至少一个碳纳米管的方法包括用电极（102）构成基板，将基板与电极浸入含有第一金属盐和第二金属的溶剂中 金属盐（104），并向所述电极施加偏置电压，使得纳米载体催化剂至少部分地与所述电极（106）上的所述基底上的所述第一金属盐和所述第二金属盐形成。 此外，形成至少一种碳纳米管的方法包括进行化学反应过程如催化分解，热解，化学气相沉积或热丝化学气相沉积o在纳米级表面上生长至少一个纳米管， 负载型催化剂（108）。

    SEMICONDUCTOR STRUCTURES AND DEVICES
    5.
    发明申请
    SEMICONDUCTOR STRUCTURES AND DEVICES 审中-公开
    半导体结构和器件

    公开(公告)号：WO03009376A3

    公开(公告)日：2003-05-01

    申请号：PCT/US0212971

    申请日：2002-04-23

    Applicant: MOTOROLA INC

    Inventor： TALIN ALBERT A ,  HILT LYNDEE L ,  DEMKOV ALEXANDER A

    IPC: H01L21/20 ,  H01L21/8258 ,  H01L27/06

    CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258

    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates (302) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers (326). An accommodating buffer layer (304) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (308) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate includes utilizing an intermetallic layer (362) of an intermetallic compound material.

    Abstract translation: 通过形成用于生长单晶层（326）的顺应性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（302），例如大硅晶片上。 容纳缓冲层（304）包括通过硅氧化物的非晶界面层（308）与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成包括利用金属间化合物材料的金属间化合物（362）。

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