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公开(公告)号:AU3587597A
公开(公告)日:1998-04-24
申请号:AU3587597
申请日:1997-07-08
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: H04L27/14 , G06F7/544 , G06F17/10 , H03H7/30 , H03M7/30 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22
Abstract: A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.
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公开(公告)号:FR2754366A1
公开(公告)日:1998-04-10
申请号:FR9710122
申请日:1997-08-07
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: G06F7/544 , G06F17/10 , H03H7/30 , H04L27/14 , H03M7/30 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22 , G06F7/52 , G06F7/02 , G06F17/15
Abstract: A filter co-processor (103, 109 and 109 fig.) within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signals (112) are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values for demodulation, the filter co-processor is able to process information in a given amount of time, leading to increased processing when compared to the prior art.
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公开(公告)号:ES2147693A1
公开(公告)日:2000-09-16
申请号:ES9702065
申请日:1997-10-03
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: G06F7/544 , G06F17/10 , H04L27/14 , H03H7/30 , H03M7/30 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22
Abstract: Un coprocesador filtro (figura 1) contenido en un Procesador de Señal Digital (DSP) se aprovecha de la naturaleza ortogonal de las señales moduladas durante el proceso de ecualización. Como, tras la recepción, únicamente ciertos valores reales/imaginarios de la señal recibida son útiles para la demodulación, el coprocesador filtro (figura 1) procesa únicamente esos valores para estimar la señal transmitida. Procesando sólo esos valores útiles para la demodulación, el coprocesador filtro (figura 1) es capaz de procesar más información en un intervalo de tiempo dado, realizando un mayor procesamiento en comparación con el arte previo.
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公开(公告)号:DE19781047B4
公开(公告)日:2005-09-29
申请号:DE19781047
申请日:1997-07-08
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: H04L27/14 , G06F7/544 , G06F17/10 , H03H7/30 , H03M7/30 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22 , H03H17/02 , H04L27/38 , G06F17/15
Abstract: A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.
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公开(公告)号:DE60007956T2
公开(公告)日:2004-07-15
申请号:DE60007956
申请日:2000-02-21
Applicant: MOTOROLA INC
Inventor: TARRAB MOSHE , ELNEKAVE MARK , TOKAR JACOB , PISEK ERAN
Abstract: A device and method for performing SISO (Soft In-Soft Out) decoding, particularly for turbo decoders, moving the forward-backward decoding approximation of MAP (Maximum a Posteriori probability) decoding. The method comprises the steps of: (a) providing a trellis representative of an output of a convolutional encoder, the convolutional encoder has a coding rate of R, the trellis having a block length T. (b) assigning an initial conditions to each starting node of the trellis for a forward iteration through the trellis. (c) computing a forward metric for each node, starting from the start of the trellis and advancing forward through the trellis and storing forward metrics of nodes of a plurality of starting stages of windows. (d) repeating stages d(1)-d(3) until all lambdas of the trellis are calculated; d(1) retrieving forward metrics of nodes of a starting stage of a window, the retrieved forward metrics were computed and stored during step (c). d(2) computing and storing forward metrics for each node, starting from a second stage of the window and ending at the ending stage of the window. d(3) computing backwards metrics for each node, starting from the ending stage of the window and ending at the starting stage of the window; wherein when backward metrics of nodes of a stage are computed and the forward metrics of the nodes of an adjacent stage were previously computed, the computation of backward metrics is integrated with the computation of lambda from the stage of the adjacent stage and a storage of the claculated lambdas in order to accelerate the decoding operation.
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公开(公告)号:RU2178949C2
公开(公告)日:2002-01-27
申请号:RU98112274
申请日:1997-07-08
Applicant: MOTOROLA INC
Inventor: KANDMANN TOMAS , MANSURI MEHK , TARRAB MOSHE , PISEK EHRAN
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公开(公告)号:GB2322057B
公开(公告)日:2001-04-25
申请号:GB9811085
申请日:1997-07-08
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: G06F7/544 , G06F17/10 , H04L27/14 , H03H7/30 , H03M7/30 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22 , H04L27/233 , H03M13/39
Abstract: A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.
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公开(公告)号:FI981263A0
公开(公告)日:1997-07-08
申请号:FI981263
申请日:1998-06-03
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: G06F7/544 , G06F17/10 , H03H7/30 , H03M7/30 , H04L27/14 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22
Abstract: A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.
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公开(公告)号:DE60007956D1
公开(公告)日:2004-03-04
申请号:DE60007956
申请日:2000-02-21
Applicant: MOTOROLA INC
Inventor: TARRAB MOSHE , ELNEKAVE MARK , TOKAR JACOB , PISEK ERAN
Abstract: A device and method for performing SISO (Soft In-Soft Out) decoding, particularly for turbo decoders, moving the forward-backward decoding approximation of MAP (Maximum a Posteriori probability) decoding. The method comprises the steps of: (a) providing a trellis representative of an output of a convolutional encoder, the convolutional encoder has a coding rate of R, the trellis having a block length T. (b) assigning an initial conditions to each starting node of the trellis for a forward iteration through the trellis. (c) computing a forward metric for each node, starting from the start of the trellis and advancing forward through the trellis and storing forward metrics of nodes of a plurality of starting stages of windows. (d) repeating stages d(1)-d(3) until all lambdas of the trellis are calculated; d(1) retrieving forward metrics of nodes of a starting stage of a window, the retrieved forward metrics were computed and stored during step (c). d(2) computing and storing forward metrics for each node, starting from a second stage of the window and ending at the ending stage of the window. d(3) computing backwards metrics for each node, starting from the ending stage of the window and ending at the starting stage of the window; wherein when backward metrics of nodes of a stage are computed and the forward metrics of the nodes of an adjacent stage were previously computed, the computation of backward metrics is integrated with the computation of lambda from the stage of the adjacent stage and a storage of the claculated lambdas in order to accelerate the decoding operation.
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公开(公告)号:FR2754366B1
公开(公告)日:2003-08-15
申请号:FR9710122
申请日:1997-08-07
Applicant: MOTOROLA INC
Inventor: KUNDMANN THOMAS , MANSOURI MACK , TARRAB MOSHE , PISEK ERAN
IPC: G06F7/544 , G06F17/10 , H03H7/30 , H04L27/14 , H03M7/30 , H04B3/06 , H04B3/14 , H04B7/005 , H04L25/03 , H04L27/06 , H04L27/22 , G06F7/52 , G06F7/02 , G06F17/15
Abstract: A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.
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