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    Sinusoidal and square wave oscillator with automatic gain control
    1.
    发明授权
    Sinusoidal and square wave oscillator with automatic gain control 失效
    具有自动增益控制的SINUSOIDAL和平方波振荡器

    公开(公告)号：US3649929A

    公开(公告)日：1972-03-14

    申请号：US3649929D

    申请日：1970-11-30

    Applicant: MOTOROLA INC

    Inventor： THOMPSON JAMES E

    IPC: H03L5/00 ,  H03B3/02 ,  H03B5/12

    CPC classification number: H03L5/00

    Abstract: There is disclosed an integrated circuit which functions as a sinusoidal and square wave generator with a direct coupled automatic gain control to vary the current through the oscillator, so as to keep the gain of the oscillator at a figure less than that at which the nonlinearity of the circuit becomes significant. The automatic gain control portion of the circuit includes half-wave rectifying and peak following circuits which follow the peak to peak voltage in the oscillator section and control the current through the oscillator as a function of this voltage. The square wave generating circuit includes a half-wave rectifying circuit and a high gain amplifying section to provide a partially clipped square wave operating below a reference potential, making the square wave signal compatible with emitter coupled logic systems.

    Abstract translation: 公开了一种集成电路，其用作具有直接耦合自动增益控制的正弦和方波发生器，以改变通过振荡器的电流，以便将振荡器的增益保持在小于非线性 电路变得显着。 电路的自动增益控制部分包括跟随振荡器部分的峰峰值电压的半波整流和峰值跟随电路，并根据该电压控制通过振荡器的电流。 方波发生电路包括半波整流电路和高增益放大部分，以提供在参考电位以下工作的部分截取的方波，使得方波信号与发射极耦合逻辑系统兼容。

    Weighted ladder technique
    2.
    发明授权
    Weighted ladder technique 失效
    加权梯级技术

    公开(公告)号：US3699568A

    公开(公告)日：1972-10-17

    申请号：US3699568D

    申请日：1970-12-21

    Applicant: MOTOROLA INC

    Inventor： THOMPSON JAMES E ,  AMATO GERALD J D

    IPC: H03M1/00 ,  H03K13/04

    CPC classification number: H03M1/00 ,  H03M1/1009

    Abstract: There is disclosed a weighted ladder network for use in digital to analog converters which s characterized by faster speeds than the common R/2R and binary ladder configurations for the same total power consumption. The technique involves splitting up a conventional ladder network into two separate sections. The first section is a conventional binary ladder driven by equal current sources. The second section, however, involves weighting the resistance elements and the current sources in such a manner that the total resistance of the circuit is minimized.

    Abstract translation: 公开了一种用于数模转换器的加权梯形网络，其特征在于比相同总功耗的公共R / 2R和二进制梯形图配置更快的速度。 该技术涉及将传统的梯形网络分成两个分开的部分。 第一部分是由等电流源驱动的常规二进制梯形图。 然而，第二部分涉及以使得电路的总电阻最小化的方式加权电阻元件和电流源。

    Sample and hold circuit
    3.
    发明授权
    Sample and hold circuit 失效
    示例和保持电路

    公开(公告)号：US3643110A

    公开(公告)日：1972-02-15

    申请号：US3643110D

    申请日：1970-11-30

    Applicant: MOTOROLA INC

    Inventor： THOMPSON JAMES E

    IPC: G11C27/00 ,  G11C27/02 ,  H03K17/60

    CPC classification number: G11C27/00 ,  G11C27/026

    Abstract: There is disclosed a sample and hold circuit employing an amplification stage which is turned ON and OFF by steering a current source between the amplification stage and current sink circuitry. This decreases the aperture time of the sample and hold circuit to such an extent that one microsecond analog to digital conversion is possible for an 8-bit system including sync pulses. The sample and hold circuit eliminates the problem of discharge of the holding capacitor through the sample and hold circuit while at the same time decreasing sample and hold aperture time.

    Phase detector and digital phase-locked loop
    5.
    发明授权
    Phase detector and digital phase-locked loop 失效
    相位检测器和数字锁相环

    公开(公告)号：US3644835A

    公开(公告)日：1972-02-22

    申请号：US3644835D

    申请日：1970-12-21

    Applicant: MOTOROLA INC

    Inventor： THOMPSON JAMES E

    IPC: H03L7/085 ,  H03D13/00

    CPC classification number: H03L7/085

    Abstract: There is disclosed a phase detector which operates in a current mode to detect the phase difference between an analog input signal and a digital input signal. The phase difference between these two signals is provided as a current generated from combined chopping and gain block circuits. Current-mode operation increases the gain obtainable from prior art voltage-mode phase detectors and enables convenient filter circuit design for integration of the output signals from the phase detector. The current-mode phase detector may be used in combination with a voltage-controlled multivibrator circuit to provide a digital phase-locked loop having a high-loop gain and having improved pull-in and hold-in ranges. The combined chopping and gain block circuits enables IC implementation with a minimum number of external connections.

    Sample and hold trigger circuit
    6.
    发明授权
    Sample and hold trigger circuit 失效
    样品和保持触发电路

    公开(公告)号：US3638041A

    公开(公告)日：1972-01-25

    申请号：US3638041D

    申请日：1970-12-02

    Applicant: MOTOROLA INC

    Inventor： THOMPSON JAMES E

    IPC: H03K3/286 ,  H03K17/00

    CPC classification number: H03K3/286

    Abstract: An integrated bistable trigger or comparator circuit normally is provided with operating current from a first current source, and the state of the trigger circuit is changed by a differential input circuit operated with a second current source providing a greater current than the first current source for altering the current drawn by the load resistors of the trigger stage to change its balance and thereby change its state. A third current source is connected to the trigger circuit in parallel with the first current source and is operative to draw a greater predetermined current than that provided by the second current source, so that when the third current source is operating, the input signals have no effect on the operation of the trigger circuit. A clock signal controlled switch is provided for disabling the third current source to permit the trigger circuit to be responsive to input signals.

    Abstract translation: 整体双稳态触发器或比较器电路通常被提供有来自第一电流源的工作电流，并且触发电路的状态由用第二电流源操作的差分输入电路改变，该第二电流源提供比第一电流源更大的电流，用于改变 由触发级的负载电阻抽取的电流改变其平衡，从而改变其状态。 第三电流源与第一电流源并联连接到触发电路，并且可操作地绘制比由第二电流源提供的电流更大的预定电流，使得当第三电流源工作时，输入信号没有 影响触发电路的运行。 提供时钟信号控制开关用于禁止第三电流源以允许触发电路响应于输入信号。

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