公开(公告)号：WO1980002881A1

公开(公告)日：1980-12-24

申请号：PCT/US1980000713

申请日：1980-06-09

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  THOMPSON R

IPC: G06F13/00

CPC classification number: G11C16/105 ,  G11C5/066 ,  G11C16/102 ,  G11C16/32

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), an EPROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and an input pin for providing a RESET signal or programming potential V u (23). An EPROM control register (53) in the CPU is loadable under the control of a computer program stored in an external memory (40). Responsive to a first bit in the EPROM control register an address buffer/latch (61) and a data latch (62) temporarily latch address and data information during a write operation to the EPROM. Responsive to a second bit in the EPROM control register the programming potential is applied to the EPROM for a predetermined time to program the data information into the EPROM at its associated address. The accuracy of the programming operation may be verified using the CPU under the control of the external computer program, to compare the address and data information programmed into the EPROM with the original source of such information.

Abstract translation: 单片机包括CPU（1），RAM（2），EPROM（3），定时器（4），串行I / O通信逻辑（5），四个I / O端口（11-14） 以及用于提供RESET信号或编程电位V u（23）的输入引脚。 在存储在外部存储器（40）中的计算机程序的控制下，CPU中的EPROM控制寄存器（53）可以被加载。 响应于EPROM控制寄存器中的第一位，地址缓冲器/锁存器（61）和数据锁存器（62）在写入操作期间将地址和数据信息临时锁存到EPROM。 响应于EPROM控制寄存器中的第二位，将编程电位施加到EPROM一段预定的时间，以将数据信息编程到其相关地址处的EPROM中。 可以使用在外部计算机程序控制下的CPU来验证编程操作的精度，将编程到EPROM中的地址和数据信息与此类信息的原始源进行比较。

公开(公告)号：DE3584150D1

公开(公告)日：1991-10-24

申请号：DE3584150

申请日：1985-04-12

Applicant: MOTOROLA INC

Inventor： MOTHERSOLE S ,  CRUDELE M ,  TIETJEN L ,  THOMPSON R

IPC: G06F9/00 ,  C07D231/12 ,  C07D231/14 ,  C07D405/00 ,  C07D405/06 ,  G06F3/00 ,  G06F12/04 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F15/00

Abstract: In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.