公开(公告)号：JPH11265311A

公开(公告)日：1999-09-28

申请号：JP30286198

申请日：1998-10-23

Applicant: MOTOROLA INC

Inventor： SNOWDEN RALPH ,  REED WENDY ,  ZOERNER GLEN JAMES ,  KWAN WAI-KIN STEVEN ,  CHU ON KI ANDREW ,  YIU HING LEUNG

IPC: G06F1/24 ,  G06F12/00 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for storing data in a dynamic random access memory(DRAM) during the period of a reset state. SOLUTION: When an external reset signal EXRST received by a reset unit 6 is asserted, an internal reset signal INRST is generated by synchronizing the signal EXRST with an internal clock and impresses the signal INRST to a CPU 4 and other modules in the circuit to reset those. During the impression of the signal INRST to the CPU 4, the rate of a refresh signal generated by a DRAM controller 7 is raised in order to refresh data stored in the DRAM 3. When the signal EXRST is disabled, a delay reset signal DLYRST is generated and impressed to the controller 7 to reset the controller 7. Since the CPU 4 has been already reset, the controller 7 is immediately reconstituted and enabled again so as to restart the refresh of the DRAM 3 so that the data in the DRAM 3 can be maintained.