公开(公告)号：WO2002099888A3

公开(公告)日：2002-12-12

申请号：PCT/US2001/048322

申请日：2001-12-11

Applicant: MOTOROLA, INC.

Inventor： IRWIN, James, S. ,  POWELL, Clinton, C. ,  JOHNSON, Timothy, J. ,  TRAYLOR, Kevin, B. ,  RABE, Duane, C. ,  BARENBURG, Barbara, Foley

IPC: H01L29/00

Abstract: A composite semiconductor (FIG. 43) (300) structure includes islands (302) of compound semiconductor materials formed on a noncompound substrate (303), and an optical testing structure. In one embodiment, a scan chain (301) runs through the noncompound substrate (303) (and possibly also through the islands (302)) and terminates in the islands at optical interface elements (304), one of which is an optical emitter and the other of which is an optical detector. A test device (FIG. 44) (400) inputs test signals to, and reads test signals from, the scan chain by interfacing (401) optically with the optical interface elements. In another embodiment (FIG. 46), an optical detector (604) is formed in the silicon substrate (52) and an optical emitter (605) is formed in the compound semiconductor material (66). A leaky waveguide (606) communicating with the emitter (605) overlies the detector (604), and detection by the detector of light (610) emitted by the emitter (605) is an indication of the absence of an intended circuit element between the detector (604) and the leaky side of the waveguide (606).

公开(公告)号：EP0480012B1

公开(公告)日：1996-07-24

申请号：EP91908982.1

申请日：1991-04-22

Applicant: MOTOROLA, INC.

Inventor： HIETALA, Alexander, W. ,  RABE, Duane, C.

IPC: H03L7/197 ,  H03C3/09

CPC classification number: H03C3/0933 ,  H03C3/0925 ,  H03L7/1976

Abstract: A fractional-N synthesizer (803) employing at least a second order sigma-delta modulator (900) is disclosed. The most significant bits from the output accumulator (1011) of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider (103). Modulation to the synthesizer is introduced as part of the digital number input to sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.

公开(公告)号：EP0480012A1

公开(公告)日：1992-04-15

申请号：EP91908982.0

申请日：1991-04-22

Applicant: MOTOROLA, INC.

Inventor： HIETALA, Alexander, W. ,  RABE, Duane, C.

IPC: H03C3 ,  H03L7 ,  H03M3 ,  H03M7

CPC classification number: H03C3/0933 ,  H03C3/0925 ,  H03L7/1976

Abstract: Un synthétiseur fractionnaire de type N (803) utilisant au moins un modulateur (900) sigma-delta de deuxième ordre est décrit. Les binaires les plus significatifs de l'accumulateur de sortie (1011) du modulateur sigma-delta sont utilisés comme commande d'exécution pour le diviseur variable du démultiplicateur à boucle (103). Le signal de modulation envoyé au synthétiseur fait partie de l'entrée numérique d'un chiffre dans le modulateur sigma-delta et la production de signaux parasites est réduite au moyen de la sélection d'un chiffre élevé comme dénominateur de la partie fractionnaire du diviseur du démultiplicateur à boucle.

公开(公告)号：WO2002099846A2

公开(公告)日：2002-12-12

申请号：PCT/US2001/050694

申请日：2001-12-27

Applicant: MOTOROLA, INC.

Inventor： FOLEY, Barbara, M. ,  RABE, Duane, C. ,  TRAYLOR, Kevin, B. ,  JOHNSON, Timothy, Joe

IPC: H01L

CPC classification number: G11B5/3103 ,  G11B5/10 ,  G11B11/10534 ,  G11B33/12 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. The compliant substrate includes an accommodating buffer layer on at least a portion of a silicon wafer (52). The accommodating buffer layer (60) is a layer of monocrystalline oxide spaced apart from the portion of the silicon wafer (52) by an amorphous interface layer (62) of silicon oxide. The amorphous interface layer (62) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (60). A device structure (51) for interacting with magnetic storage media (110) is formed overlying the monocrystalline substrate (52). Portions or an entirety of the device structure (51) can also overly the accommodating buffer layer (60), or the monocrystalline material layer (52).

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 柔性衬底包括在硅晶片（52）的至少一部分上的容纳缓冲层。 容纳缓冲层（60）是通过硅氧化物的非晶界面层（62）与硅晶片（52）的部分间隔开的单晶氧化物层。 非晶界面层（62）耗散应变并允许高质量单晶氧化物容纳缓冲层（60）的生长。 用于与磁存储介质（110）相互作用的器件结构（51）形成在单晶衬底（52）上。 部分或整个装置结构（51）也可以过度地覆盖容纳缓冲层（60）或单晶材料层（52）。

公开(公告)号：WO1992011703A1

公开(公告)日：1992-07-09

申请号：PCT/US1991009584

申请日：1991-12-18

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  RABE, Duane, C. ,  FELDT, Daniel, C.

IPC: H04B01/10

CPC classification number: H04B1/30 ,  H03D3/008 ,  H04L25/062 ,  H04L25/063 ,  H04L27/22 ,  H04L27/2332

Abstract: A radio receiver having at least two operational states and including a variable gain amplifier and at least two adaptive DC offset compensators (421, 427) to suppress undesired DC offset. The first operational state of the radio receiver (121) adjusts the adaptive DC offset compensator circuits (421, 427) to appropriate output levels in absence of an input signal to the radio receiver (121). The second operational state receives the input signal through the radio receiver (121) and eliminates the undesired DC offset (309) from the received input signal with the adaptive DC offset compensator circuits (421, 427) and allows the received input signals to be processed.

公开(公告)号：WO2002099898A3

公开(公告)日：2002-12-12

申请号：PCT/US2001/049484

申请日：2001-12-27

Applicant: MOTOROLA, INC.

Inventor： JOHNSON, Timothy, Joe ,  TRAYLOR, Kevin, B. ,  RABE, Duane, C. ,  BARENBURG, Barbara, Foley

IPC: H01L31/173

Abstract: High quality epitaxial layers of monocrystalline materials (132, 166, 170) can be grown overlying monocrystalline substrates (110, 161, 3811) by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer (124, 164) that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (122, 162) of silicon oxide. The amorphous interface layer (122, 162) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (124, 164. In this way, an integrated circuit (3810, 160, 4200) that distributes its clock signals optically is provided. The integrated circuit (3810, 160, 4200) preferably includes a plurality of digital CMOS circuits (181, 3813) that communicate optically. The optical devices (180, 3814, 3815) are preferably formed from compound semiconductor structures (3812).

公开(公告)号：WO2002099898A2

公开(公告)日：2002-12-12

申请号：PCT/US2001/049484

申请日：2001-12-27

Applicant: MOTOROLA, INC.

Inventor： JOHNSON, Timothy, Joe ,  TRAYLOR, Kevin, B. ,  RABE, Duane, C. ,  BARENBURG, Barbara, Foley

IPC: H01L31/173

CPC classification number: G02B6/132 ,  G02B6/12004 ,  G02B6/43 ,  G02B2006/12107 ,  G02B2006/12169 ,  G06F1/105 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials (132, 166, 170) can be grown overlying monocrystalline substrates (110, 161, 3811) by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer (124, 164) that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (122, 162) of silicon oxide. The amorphous interface layer (122, 162) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (124, 164. In this way, an integrated circuit (3810, 160, 4200) that distributes its clock signals optically is provided. The integrated circuit (3810, 160, 4200) preferably includes a plurality of digital CMOS circuits (181, 3813) that communicate optically. The optical devices (180, 3814, 3815) are preferably formed from compound semiconductor structures (3812).

Abstract translation: 通过形成用于生长单晶层的顺应性衬底，可以将单晶材料（132,166,170）的高质量外延层生长成覆盖在单晶衬底（110,161,3891）上。 实现符合性的一种方式包括首先在硅晶片上生长容纳缓冲层（124,164），其是通过氧化硅的非晶界面层（122,162）与硅晶片间隔开的单晶氧化物层。 非晶界面层（122,162）耗散应变并允许高质量单晶氧化物容纳缓冲层（124,164）的生长。以这种方式，以光学方式分配其时钟信号的集成电路（3810,160,4200）是 集成电路（3810,160,4200）优选地包括以光学方式通信的多个数字CMOS电路（181,3813），光学器件（180,3814,3815）优选地由化合物半导体结构（3812）形成。

公开(公告)号：WO2002099858A1

公开(公告)日：2002-12-12

申请号：PCT/US2001/050689

申请日：2001-12-27

Applicant: MOTOROLA, INC.

Inventor： FOLEY, Barbara, M. ,  RABE, Duane, C. ,  TRAYLOR, Kevin, B. ,  JOHNSON, Timothy, Joe

IPC: H01L21/20

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. The compliant substrate includes an accommodating buffer layer over a portion of a silicon wafer (254). The accommodating buffer layer (260) is a layer of monocrystalline oxide spaced apart from the portion of silicon wafer by an amorphous interface layer (262) of silicon oxide. The amorphous interface layer (262) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (260). A device structure (250) for interacting with optical storage media (300) is formed overlying the portion of silicon wafer (254). Portions or an entirety of the device structure (250) can also overly the accommodating buffer layer (260) , or the portion of the silicon wafer (254).

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 柔性衬底包括在硅晶片（254）的一部分上的容纳缓冲层。 容纳缓冲层（260）是通过氧化硅的非晶界面层（262）与硅晶片的部分间隔开的单晶氧化物层。 非晶界面层（262）耗散应变并允许高质量单晶氧化物容纳缓冲层（260）的生长。 用于与光学存储介质（300）相互作用的器件结构（250）形成在硅晶片（254）的一部分上方。 部分或整个器件结构（250）也可以过度地覆盖容纳缓冲层（260）或硅晶片（254）的部分。

公开(公告)号：WO1992004766A1

公开(公告)日：1992-03-19

申请号：PCT/US1991005455

申请日：1991-08-01

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  HIETALA, Alexander, W. ,  RABE, Duane, C.

IPC: H03C03/09

CPC classification number: H03L7/1976

Abstract: A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of the accumulators (615, 617) are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.

公开(公告)号：WO1991007829A1

公开(公告)日：1991-05-30

申请号：PCT/US1990006389

申请日：1990-11-07

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  LABEDZ, Gerald, P. ,  ATKINSON, Frederick, G. ,  RABE, Duane, C. ,  SCHULER, Joseph, J. ,  WERRONEN, Alton, P.

IPC: H04B07/08

CPC classification number: H04B7/0845 ,  H04B7/084 ,  H04B7/0857 ,  H04B7/0888 ,  H04L1/06

Abstract: A method and apparatus for diversity reception in a communication system is provided. A dual branch receiver (102, 103) is provided with a stored replica of expected reference information so that correlation with received time-dispersed signals (100, 101) produces an estimate of the transmission channel's impulse response as seen by each branch, and determines, among other things, phase error between the branch local oscillators and the time-dispersed signals. Matched filters (214, 215) are constructed which then coherently align the time-dispersed signals from each branch with that branch's local oscillator (208, 209) which constitutes a part of the signal equalization. A diversity processor (105) performs bit by bit selection on the re-aligned signals, maximal ratio combining of the re-aligned signals, or equal gain combining of the re-aligned signals, followed by a sequence estimation which uses similarly selected or combined channel distortion compensation parameters to complete the equalization process on the new signal.