公开(公告)号：US20130300593A1

公开(公告)日：2013-11-14

申请号：US13941598

申请日：2013-07-15

Applicant: MediaTek Inc.

Inventor： Yun-Shiang SHU

IPC: H03M1/50

CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

Abstract translation: 提供比较电路并包括第一和第二比较器和第一时间 - 数字比较器。 具有第一偏移电压的第一比较器接收输入信号并产生第一比较信号和第一反比较信号。 第二比较器接收输入信号并产生第二比较信号和第二反比较信号。 第一偏移电压大于第二偏移电压。 第一时间数字比较器接收第一比较信号和第二反比较信号，并根据第一比较信号和第二反比较信号产生第一和第二确定信号。 第一和第二确定信号指示输入信号的电压是否大于第一中间电压。 第一中间电压等于第一偏移电压和第二偏移电压之和的一半。

公开(公告)号：US20200343905A1

公开(公告)日：2020-10-29

申请号：US16837417

申请日：2020-04-01

Applicant: MEDIATEK INC.

Inventor： Yun-Shiang SHU ,  Su-Hao WU ,  Hung-Yi HSIEH ,  Albert Yen-Chih CHIOU

IPC: H03M3/00

Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.

公开(公告)号：US20150015307A1

公开(公告)日：2015-01-15

申请号：US14504787

申请日：2014-10-02

Applicant: MediaTek Inc.

Inventor： Yun-Shiang SHU

IPC: H03K5/24 ,  H03F3/45

CPC classification number: H03K5/2481 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45197 ,  H03F2203/45424 ,  H03F2203/45466 ,  H03F2203/45482 ,  H03F2203/45492 ,  H03K5/2472 ,  H03K5/249

Abstract: A comparator has a differential pair circuit and a current control circuit. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors. An amplifier circuit is also disclosed, having a differential pair circuit, a current control circuit, an amplification circuit and a reset circuit.

Abstract translation: 比较器具有差分对电路和电流控制电路。 差分对电路具有第一和第二比较器晶体管，并且被布置为根据时钟信号比较第一输入和第二输入，以产生指示第一和第二输入的差是否超过内部偏移的结果。 电流控制电路与差分对电路串联耦合，并且被配置为提供对第一和第二比较器晶体管的拉电流的不相等的能力。 还公开了具有差分对电路，电流控制电路，放大电路和复位电路的放大器电路。