公开(公告)号：EP2073396A3

公开(公告)日：2011-06-08

申请号：EP08169998.5

申请日：2008-11-26

Applicant: Mediatek Inc.

Inventor： Mestechkin, Russ ,  Mathew, Deepak ,  Wang, Justin ,  Nandipaku, Sanjay

IPC: H04B1/707

CPC classification number: H04B1/707 ,  H04B2201/70707

Abstract: A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set oftime slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.

Abstract translation: 无线系统具有上行链路码片速率处理架构，其中提供至少两组寄存器，每组寄存器存储一组时隙配置参数。 存储器存储一系列时隙配置集标识符，每个时标配置集标识符标识一组寄存器，每个标识符对应于一个时隙。 码片速率处理单元处理多个时隙中的数据流，其中在每个时隙处，并且码片速率处理单元根据存储在与该时隙相关联的寄存器组中的时隙配置参数组来配置 时隙对应的时隙配置集标识。

公开(公告)号：EP2073396A2

公开(公告)日：2009-06-24

申请号：EP08169998.5

申请日：2008-11-26

Applicant: Mediatek Inc.

Inventor： Mestechkin, Russ ,  Mathew, Deepak ,  Wang, Justin ,  Nandipaku, Sanjay

IPC: H04B1/707

CPC classification number: H04B1/707 ,  H04B2201/70707

Abstract: A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set oftime slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.

Abstract translation: 无线系统具有其中提供至少两组寄存器的上行链路码片速率处理架构，每组寄存器存储一组时隙配置参数。 存储器存储一系列时隙配置集标识符，每个识别寄存器组中的一个，每个标识符对应于时隙。 芯片速率处理单元在多个时隙中处理数据流，其中在每个时隙处，并且芯片速率处理单元根据存储在与所述时隙相关联的寄存器组中的时隙配置参数的集合来配置 与时隙对应的时隙配置集标识符。