Method and apparatus for gather/scatter operations in a vector processor

    公开(公告)号:US12175116B2

    公开(公告)日:2024-12-24

    申请号:US17669995

    申请日:2022-02-11

    Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.

    Method and apparatus for desynchronizing execution in a vector processor

    公开(公告)号:US11782871B2

    公开(公告)日:2023-10-10

    申请号:US17701582

    申请日:2022-03-22

    CPC classification number: G06F15/8061

    Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

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