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公开(公告)号：US10983931B2
公开(公告)日：2021-04-20
申请号：US15141823
申请日：2016-04-29
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Bryan Kris , Calum Wilkie , Jason Sachs , Andreas Reiter
Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
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公开(公告)号：US20160321202A1
公开(公告)日：2016-11-03
申请号：US15141823
申请日：2016-04-29
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Bryan Kris , Calum Wilkie , Jason Sachs , Andreas Reiter
CPC classification number: G06F13/1673 , G06F9/30043 , G06F9/3877 , G06F9/3879 , G06F12/14 , G06F13/4068 , G06F2212/1052
Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
Abstract translation: 集成电路具有主处理核心，其具有与非易失性存储器耦合的中央处理单元和独立于主处理核心并具有与易失性程序存储器耦合的中央处理单元操作的从属处理核心，其中主中央处理单元 被配置为将程序指令传送到从处理核心的非易失性存储器，并且其中通过在主处理核心的中央处理单元内执行专用指令来执行程序指令的传送。
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公开(公告)号：US20240275366A1
公开(公告)日：2024-08-15
申请号：US18432347
申请日：2024-02-05
Applicant: Microchip Technology Incorporated
Inventor： Yong Yuenyongsgool , Andreas Reiter , Stephen Bowling , Jason Sachs
IPC: H03K3/017
CPC classification number: H03K3/017
Abstract: An apparatus includes a pulsed-width modulation (PWM) generator circuit to generate generally complementary PWM signals. The signals are to prevent two complementary switches that receive the complementary PWM signals from both being activated at a same time. The PWM signals are generally complementary with respect to their active portions. The apparatus includes an override circuit to override at least one of the complementary PWM signals to yield adjusted PWM signals. The adjusted PWM signals are to cause the two complementary switches to be activated at a same time when the adjusted PWM signals are received at the two complementary switches.
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公开(公告)号：US10776292B2
公开(公告)日：2020-09-15
申请号：US16250274
申请日：2019-01-17
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Bryan Kris , Calum Wilkie , Jason Sachs , Andreas Reiter
Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
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公开(公告)号：US10771012B2
公开(公告)日：2020-09-08
申请号：US16587509
申请日：2019-09-30
Applicant: Microchip Technology Incorporated
Inventor： Jason Sachs
Abstract: An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190188163A1
公开(公告)日：2019-06-20
申请号：US16250274
申请日：2019-01-17
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Bryan Kris , Calum Wilkie , Jason Sachs , Andreas Reiter
CPC classification number: G06F13/1673 , G06F9/30043 , G06F9/3877 , G06F9/3879 , G06F12/14 , G06F13/4068 , G06F2212/1052
Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
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公开(公告)号：US20230176866A1
公开(公告)日：2023-06-08
申请号：US17982980
申请日：2022-11-08
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Ashish Desai , Jason Sachs , Calum Wilkie
IPC: G06F9/30
CPC classification number: G06F9/30032 , G06F9/30123
Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
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公开(公告)号：US11082544B2
公开(公告)日：2021-08-03
申请号：US16169501
申请日：2018-10-24
Applicant: Microchip Technology Incorporated
Inventor： Jason Sachs
Abstract: Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.
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公开(公告)号：US10439556B2
公开(公告)日：2019-10-08
申请号：US15491803
申请日：2017-04-19
Applicant: Microchip Technology Incorporated
Inventor： Jason Sachs
Abstract: An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.
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10.发明申请公开(公告)号：US20190281144A1
公开(公告)日：2019-09-12
申请号：US16169501
申请日：2018-10-24
Applicant: Microchip Technology Incorporated
Inventor： Jason Sachs
Abstract: Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.
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