公开(公告)号：US20240069748A1

公开(公告)日：2024-02-29

申请号：US18219023

申请日：2023-07-06

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Yang Liu ,  Jiangli Zhu ,  Juane Li ,  Aaron Lee

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679

Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page. The processing device further performs a second media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by the respective management unit, and responsive to determining that a value of the data state metric of a memory page of the plurality of memory page addressable by the mandatory wordline satisfies the specified condition, performs a second media management operation with respect to the management unit containing the memory page.

公开(公告)号：US20240177795A1

公开(公告)日：2024-05-30

申请号：US18519248

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Aaron Lee ,  Zhenming Zhou ,  Murong Lang

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

Abstract: A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

公开(公告)号：US20240071462A1

公开(公告)日：2024-02-29

申请号：US18227139

申请日：2023-07-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Yang Liu ,  Juane Li ,  Aaron Lee ,  Jiangli Zhu

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C11/4096

Abstract: A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.

公开(公告)号：US20250078939A1

公开(公告)日：2025-03-06

申请号：US18771819

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Yang Liu ,  Steven Michael Kientz ,  Tingjun Xie ,  Aaron Lee ,  Jiangli Zhu ,  Wei Wang

IPC: G11C16/34 ,  G11C29/52

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan operation on a plurality of block families of the memory device. Each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. The processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. The processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals. Based on the scan result, two or the plurality of block families which are scanned within the same or different intervals can be combined and thus release block family memory if their measurement results satisfy combining criterion.

公开(公告)号：US20250006270A1

公开(公告)日：2025-01-02

申请号：US18753662

申请日：2024-06-25

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Aaron Lee ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/08 ,  G11C29/52

Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells addressable by a first wordline of a first plane of the memory device. The processing device identifies a predefined index shift value associated with the first wordline. The processing device determines, by applying the predefined index shift value to a first index value of the first wordline, a second index value of a second wordline of a second plane of the memory device. The processing device further performs a second programming operation on a second set of cells addressable by the second wordline of the second plane.

公开(公告)号：US20240192875A1

公开(公告)日：2024-06-13

申请号：US18519611

申请日：2023-11-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yang Liu ,  Wenyen Chang ,  Wei Wang ,  Aaron Lee ,  Jiangli Zhu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679

Abstract: A system includes a memory device having a plurality of memory planes and a processing device operatively coupled with the memory device. The processing device to is perform operations including identifying a first block stripe of the memory device. The first block stripe includes a first plurality of blocks arranged across the plurality of memory planes. The operations further include determining that the first plurality of blocks of the first block stripe has greater than a threshold number of blocks associated with an error condition. Responsive to determining that the first plurality of blocks has greater than the threshold number of blocks associated with the error condition, the operations further include mapping a block of the first plurality of blocks associated with the error condition to a second block stripe including a second plurality of blocks having fewer than the threshold number of blocks associated with the error condition.