公开(公告)号：US11942159B2

公开(公告)日：2024-03-26

申请号：US17591510

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/225 ,  G11C16/32

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

公开(公告)号：US20240428862A1

公开(公告)日：2024-12-26

申请号：US18748679

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Taehyun Kim ,  Brian Kwon ,  Dong Kyo Shim ,  Kwang Ho Kim ,  Erwin E. Yu ,  Fulvio Rori

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

公开(公告)号：US20240203508A1

公开(公告)日：2024-06-20

申请号：US18589730

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/225 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.

公开(公告)号：US20230063656A1

公开(公告)日：2023-03-02

申请号：US17591510

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32 ,  G06F3/06

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.