公开(公告)号：US20230345708A1

公开(公告)日：2023-10-26

申请号：US17729450

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Terrence B. McDaniel ,  Russell A. Benson ,  Vinay Nair

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10888 ,  H01L27/10897

Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.

公开(公告)号：US20190221366A1

公开(公告)日：2019-07-18

申请号：US16368601

申请日：2019-03-28

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Hiroshi Amaike ,  Kota Hattori

IPC: H01G4/005 ,  H01G4/018

CPC classification number: H01G4/005 ,  H01G4/012 ,  H01G4/018 ,  H01G4/33 ,  H01G4/40 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/87 ,  H01L28/91

Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.

公开(公告)号：US20170330882A1

公开(公告)日：2017-11-16

申请号：US15151503

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/027

CPC classification number: H01L27/10823 ,  H01L21/0273 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US20170213834A1

公开(公告)日：2017-07-27

申请号：US15002401

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/11582 ,  H01L28/00 ,  H01L2924/1436

Abstract: A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.

公开(公告)号：US10566332B2

公开(公告)日：2020-02-18

申请号：US16192097

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh D. Tang

IPC: H01L27/108 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US10566136B2

公开(公告)日：2020-02-18

申请号：US16368601

申请日：2019-03-28

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Hiroshi Amaike ,  Kota Hattori

IPC: H01G4/40 ,  H01G4/005 ,  H01G4/018

Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.

公开(公告)号：US20190172517A1

公开(公告)日：2019-06-06

申请号：US16267087

申请日：2019-02-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/402 ,  G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10163909B2

公开(公告)日：2018-12-25

申请号：US15840972

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L21/027 ,  H01L21/762 ,  H01L23/528 ,  H01L27/108 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US20180102366A1

公开(公告)日：2018-04-12

申请号：US15840972

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L21/027 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L27/10823 ,  H01L21/0273 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US09859284B2

公开(公告)日：2018-01-02

申请号：US15002401

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/11582 ,  H01L28/00 ,  H01L2924/1436

Abstract: A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.