公开(公告)号：US20240371749A1

公开(公告)日：2024-11-07

申请号：US18777079

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Xiaojiang Guo ,  Naveen Kaushik ,  Shuai Xu ,  June Lee

IPC: H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

公开(公告)号：US12080756B2

公开(公告)日：2024-09-03

申请号：US17647912

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Gaurav Musalgaonkar ,  Naveen Kaushik ,  Sonam Jain ,  Haitao Liu ,  Chittoor Ranganathan Parthasarathy

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0626 ,  H01L27/088 ,  H01L29/66681 ,  H01L29/7816

Abstract: An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11728263B2

公开(公告)日：2023-08-15

申请号：US17681377

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Yoshihiko Kamata ,  Richard J. Hill ,  Kyle A. Ritter ,  Tomoko Ogura Iwasaki ,  Haitao Liu

IPC: H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5225 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

公开(公告)号：US20220238431A1

公开(公告)日：2022-07-28

申请号：US17161313

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Sidhartha Gupta ,  Pankaj Sharma ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/48

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20230276624A1

公开(公告)日：2023-08-31

申请号：US17682514

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Naveen Kaushik ,  Sidhartha Gupta

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L29/41 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/0483 ,  H01L29/42344 ,  H01L29/40117 ,  H01L29/413 ,  H01L29/517

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.

公开(公告)号：US20230223434A1

公开(公告)日：2023-07-13

申请号：US17647912

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Gaurav Musalgaonkar ,  Naveen Kaushik ,  Sonam Jain ,  Haitao Liu ,  Chittoor Ranganathan Parthasarathy

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0626 ,  H01L27/088 ,  H01L29/7816 ,  H01L29/66681

Abstract: An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20220384242A1

公开(公告)日：2022-12-01

申请号：US17818317

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  David Ross Economy ,  Richard J. Hill ,  Kyle A. Ritter ,  Naveen Kaushik

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

公开(公告)号：US20220181254A1

公开(公告)日：2022-06-09

申请号：US17681377

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Yoshihiko Kamata ,  Richard J. Hill ,  Kyle A. Ritter ,  Tomoko Ogura Iwasaki ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

公开(公告)号：US20220036927A1

公开(公告)日：2022-02-03

申请号：US17501940

申请日：2021-10-14

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey

IPC: G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12137553B2

公开(公告)日：2024-11-05

申请号：US17395211

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma

IPC: H10B41/27 ,  H01L23/538 ,  H10B43/27

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.