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公开(公告)号：US20240202114A1
公开(公告)日：2024-06-20
申请号：US18591777
申请日：2024-02-29
Applicant: Micron Technology, Inc.
Inventor： Xiangyu Tang , David Ebsen , Ying Huang , Sundararajan Sankaranarayanan
CPC classification number: G06F12/0253 , G06F3/0604 , G06F3/0652 , G06F3/0679
Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.
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公开(公告)号：US20230393750A1
公开(公告)日：2023-12-07
申请号：US18049973
申请日：2022-10-26
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0611 , G06F3/0659 , G06F3/0679
Abstract: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.
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公开(公告)号：US11556258B1
公开(公告)日：2023-01-17
申请号：US17379118
申请日：2021-07-19
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
Abstract: A processing device in a memory system identifies, while the memory device is in a first state condition, a plurality of workload conditions associated with the memory device, wherein the plurality of workload conditions comprise data reflecting a performance condition of the memory device. The processing device determines, while the memory device is in the first state condition, a host rate of a host system write performance for the memory device based on one or more workload conditions of the plurality of workload conditions. The processing device determines that one or more workload conditions of the plurality of workload conditions satisfies a first threshold criterion. Responsive to determining that the one or more workload conditions of the plurality of workload conditions satisfies the first threshold criterion, the processing device detects a change in a condition of the memory device from the first state to a second state. The processing device determines, while the memory device is in the second state condition, an adjusted host rate based on the host rate and a calculated adjustment value. The processing device uses the adjusted host rate to determine a credit consuming rate for a host write operation for the memory device.
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公开(公告)号：US20240354006A1
公开(公告)日：2024-10-24
申请号：US18759793
申请日：2024-06-28
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0611 , G06F3/0659 , G06F3/0679
Abstract: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.
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公开(公告)号：US11960740B2
公开(公告)日：2024-04-16
申请号：US18077762
申请日：2022-12-08
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
CPC classification number: G06F3/0634 , G06F3/0617 , G06F3/0635 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F12/0253
Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.
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Patent Agency Ranking
公开(公告)号：US20230102577A1
公开(公告)日：2023-03-30
申请号：US18077762
申请日：2022-12-08
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.
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公开(公告)号：US12050776B2
公开(公告)日：2024-07-30
申请号：US18049973
申请日：2022-10-26
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0611 , G06F3/0659 , G06F3/0679
Abstract: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.
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公开(公告)号：US11947452B2
公开(公告)日：2024-04-02
申请号：US17830047
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Xiangyu Tang , David Ebsen , Ying Huang , Sundararajan Sankaranarayanan
CPC classification number: G06F12/0253 , G06F3/0604 , G06F3/0652 , G06F3/0679
Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.
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公开(公告)号：US20230013757A1
公开(公告)日：2023-01-19
申请号：US17379118
申请日：2021-07-19
Applicant: Micron Technology, Inc.
Inventor： Ying Huang , Mark Ish
Abstract: A processing device in a memory system identifies, while the memory device is in a first state condition, a plurality of workload conditions associated with the memory device, wherein the plurality of workload conditions comprise data reflecting a performance condition of the memory device. The processing device determines, while the memory device is in the first state condition, a host rate of a host system write performance for the memory device based on one or more workload conditions of the plurality of workload conditions. The processing device determines that one or more workload conditions of the plurality of workload conditions satisfies a first threshold criterion. Responsive to determining that the one or more workload conditions of the plurality of workload conditions satisfies the first threshold criterion, the processing device detects a change in a condition of the memory device from the first state to a second state. The processing device determines, while the memory device is in the second state condition, an adjusted host rate based on the host rate and a calculated adjustment value. The processing device uses the adjusted host rate to determine a credit consuming rate for a host write operation for the memory device.
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公开(公告)号：US20230393976A1
公开(公告)日：2023-12-07
申请号：US17830047
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Xiangyu Tang , David Ebsen , Ying Huang , Sundararajan Sankaranarayanan
CPC classification number: G06F12/0253 , G06F3/0652 , G06F3/0604 , G06F3/0679
Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.
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