公开(公告)号：US12001340B2

公开(公告)日：2024-06-04

申请号：US18124447

申请日：2023-03-21

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891 ,  G06F13/16 ,  G11C16/06

CPC classification number: G06F12/0891 ,  G06F11/14 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0882 ,  G06F13/1668 ,  G11C16/06

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US11798601B2

公开(公告)日：2023-10-24

申请号：US17541009

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： Jonathan Wen Jian Oh ,  Allison Jayne Olson ,  Fulvio Rori ,  Qisong Lin ,  Preston A. Thomson

IPC: G11C7/10 ,  G06F12/0882 ,  G06F9/30 ,  G06F11/27

CPC classification number: G11C7/1084 ,  G06F9/30101 ,  G06F9/30189 ,  G06F11/27 ,  G06F12/0882 ,  G11C7/106 ,  G11C7/1057 ,  G11C7/1087

Abstract: A programmable memory device includes a ROM block to store instructions associated with functionality of the programmable memory device, a memory array having reserved pages to store updates to be performed on the ROM block, and a controller coupled to the ROM block and the memory array. The controller is to, in response to receipt of a remote command from a vendor server via a host system, execute the instructions to perform operations including: executing a set features command to access the set of reserved pages, as an extension to one time programmable mode; programming a set of sub-feature parameters to a specified feature address of the reserved pages, where the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and programming a REM-profiled page of the reserved pages with REM data received from the vendor server via the host system.

公开(公告)号：US11789738B2

公开(公告)日：2023-10-17

申请号：US17986318

申请日：2022-11-14

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Douglas Eugene Majerus ,  Qisong Lin

IPC: G06F9/30 ,  G06F9/445 ,  G06F3/06 ,  G06F8/65

CPC classification number: G06F9/30181 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F8/65 ,  G06F9/445

Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

公开(公告)号：US20230019189A1

公开(公告)日：2023-01-19

申请号：US17952927

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

公开(公告)号：US11500637B2

公开(公告)日：2022-11-15

申请号：US16902009

申请日：2020-06-15

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Douglas Eugene Majerus ,  Qisong Lin

IPC: G06F9/30 ,  G06F9/445 ,  G06F3/06 ,  G06F8/65

Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

公开(公告)号：US20220351786A1

公开(公告)日：2022-11-03

申请号：US17868685

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Qisong Lin ,  Shane Nowell ,  Mustafa N. Kaynak

IPC: G11C16/34 ,  G06F11/07 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  G06F3/06 ,  G11C29/00

Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

公开(公告)号：US20220254418A1

公开(公告)日：2022-08-11

申请号：US17168970

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US11366760B2

公开(公告)日：2022-06-21

申请号：US16817384

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Abdelhakim Alhussien ,  Jiangang Wu ,  Karl D. Schuh ,  Qisong Lin ,  Jung Sheng Hoei

IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/02 ,  G11C11/408 ,  G06F9/30 ,  G06F9/4401

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

公开(公告)号：US20220093145A1

公开(公告)日：2022-03-24

申请号：US17541009

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： Jonathan Wen Jian Oh ,  Aaron James Olson ,  Fulvio Rori ,  Qisong Lin ,  Preston A. Thomson

IPC: G11C7/10 ,  G06F9/30 ,  G06F12/0882 ,  G06F11/27

Abstract: A programmable memory device includes a ROM block to store instructions associated with functionality of the programmable memory device, a memory array having reserved pages to store updates to be performed on the ROM block, and a controller coupled to the ROM block and the memory array. The controller is to, in response to receipt of a remote command from a vendor server via a host system, execute the instructions to perform operations including: executing a set features command to access the set of reserved pages, as an extension to one time programmable mode; programming a set of sub-feature parameters to a specified feature address of the reserved pages, where the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and programming a REM-profiled page of the reserved pages with REM data received from the vendor server via the host system.

公开(公告)号：US20210397509A1

公开(公告)日：2021-12-23

申请号：US15733561

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Sho Chun Shi

IPC: G06F11/07

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.