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    DEVICE PACKAGES INCLUDING COMMAND/ADDRESS CONNECTIONS, AND RELATED ELECTRONIC SYSTEMS
    1.
    发明申请
    DEVICE PACKAGES INCLUDING COMMAND/ADDRESS CONNECTIONS, AND RELATED ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20250046710A1

    公开(公告)日：2025-02-06

    申请号：US18755055

    申请日：2024-06-26

    Applicant: Micron Technology Inc.

    Inventor： Scott Smith ,  Travis M. Jensen

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

    Abstract: An assembly includes a first die, and a second die arranged face-to-face with the first die. The first die includes a first pad, a second pad at a vertical elevation of the first pad, and mirror function circuitry configured to swap functionalities of the first pad and the second pad. The second die includes an additional first pad corresponding to the first pad of the first die, and an additional second pad at a vertical elevation of the additional first pad and corresponding to the second pad of the first die. The additional first pad is coupled to the second pad of the first die. The additional second pad is coupled to the first pad of the first die. Additional assemblies and electronic systems are also described.

    MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME
    2.
    发明申请
    MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME 有权
    存储器件命令解码系统和存储器件以及使用该处理器的系统

    公开(公告)号：US20160189763A1

    公开(公告)日：2016-06-30

    申请号：US15063140

    申请日：2016-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

    IPC: G11C11/4076

    CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

    Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

    Abstract translation: 公开了系统，装置和方法。 在一种这样的方法的实施例中，一种对接收到的命令信号进行解码的方法，该方法包括将接收的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合地解码，以产生多个存储器 控制信号。 接收到的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合表示存储器命令。 此外，在时钟信号的第二时钟沿提供给存储器地址节点的信号不与所接收的命令信号组合解码。 存储器命令可以是减少功率命令和/或无操作命令。

    METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT
    4.
    发明申请
    METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT 审中-公开
    用于检测时钟同步电路的锁定状态的方法，电路和系统

    公开(公告)号：US20150130521A1

    公开(公告)日：2015-05-14

    申请号：US14599265

    申请日：2015-01-16

    Applicant: Micron Technology, Inc.

    Inventor： Tyler Gomm ,  Kang Yong Kim ,  Scott Smith ,  Jongtae Kwak

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  H03L7/0802 ,  H03L7/0812 ,  H03L7/095

    Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

    Abstract translation: 描述了用于检测时钟同步电路的锁定或同步状态的锁定状态检测电路，设备，系统和方法。 检测锁定状态包括电路，该电路包括相位检测器，该相位检测器被配置为响应于表示外部时钟信号的前向路径信号与表示输出时钟信号的反馈路径信号的比较而产生延迟调整信号。 电路还包括可操作地耦合到延迟调整信号并被配置为产生指示外部时钟信号和输出时钟信号之间的同相稳态的锁定信号的趋势检测器。

    Memory device command receiving and decoding methods
    10.
    发明授权
    Memory device command receiving and decoding methods 有权

    公开(公告)号：US10127969B2

    公开(公告)日：2018-11-13

    申请号：US15456164

    申请日：2017-03-10

    Applicant: Micron Technology, Inc.

    Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

    IPC: G11C11/4076 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408

    Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

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