公开(公告)号：WO1982001429A1

公开(公告)日：1982-04-29

申请号：PCT/US1981001340

申请日：1981-10-05

Applicant: NCR CORP

Inventor： NCR CORP ,  ARMSTRONG ROLFE D

IPC: G06F09/00

CPC classification number: G06F9/4486

Abstract: A stack (30) is provided in a pipelined data processor having a plurality of control registers including a fetch control register and an execution control register associated with respective stages of the processor. The stack comprises a memory stack (303), an address register (304), and a counter-register (302) interposed between the memory stack and the control registers of the data processor. In order to speed up operation of the stack, the counterregister (302) is always made to store the latest entry into the memory stack (303), that is the top of the stack, such that the latest entry into the stack (303) is immediately available to the control registers of the data processor thereby eliminating a memory access to the stack (303).

Abstract translation: 在具有多个控制寄存器的流水线数据处理器中提供堆栈（30），该控制寄存器包括与处理器的各个级相关联的获取控制寄存器和执行控制寄存器。 堆叠包括插入在存储器堆栈和数据处理器的控制寄存器之间的存储器堆栈（303），地址寄存器（304）和计数器寄存器（302）。 为了加快堆栈的操作，总是使得计数器寄存器（302）将最新条目存储到作为堆栈顶部的存储堆栈（303）中，使得最新进入堆栈（303） 立即可用于数据处理器的控制寄存器，从而消除对堆栈的存储器访问（303）。