公开(公告)号：WO1982001380A1

公开(公告)日：1982-04-29

申请号：PCT/US1981001410

申请日：1981-10-19

Applicant: NCR CORP

Inventor： NCR CORP ,  BROWER RONALD W

IPC: C22B21/00

CPC classification number: H01L21/823871 ,  H01L21/0271 ,  H01L21/2255 ,  H01L21/768

Abstract: In a process for forming a CMOS integrated circuit structure having polysilicon gates (18, 24) and interconnections (19) which are all of the same conductivity type, preferably n s-type, polys ilicon is formed into the gate (18) for the n-FET, a barrier layer (20) for the p-FET region (15) and the interconnection pattern (19). Then a layer of arsenosilicate glass (ASG) (23) is formed over the n-FET active region (14), the interconnections (19) and in an area to define the p-FET gate (24) which is etched using the ASG layer (23) as a mask. The device is heated to drive in impurities from the ASG layer (23) to n s dope the polysilicon and form the n-FET source and drain (27, 28). Boron is then implanted into the p-FET source and drain (25, 26), the ASG layer serving to mask the polysilicon from p-type doping. Since the polysilicon which is etched is undoped, highly accurate self alignment is obtained.

Abstract translation: 在形成具有全部相同导电类型的多晶硅栅极（18,24）和互连（19）的CMOS集成电路结构的工艺中，优选为n + s型，多晶硅形成于栅极（18） ），用于p-FET区（15）的阻挡层（20）和互连图案（19）。 然后在n-FET有源区（14），互连（19）和限定使用ASG蚀刻的p-FET栅极（24）的区域中形成一层砷硅酸盐玻璃（ASG）（23） 层（23）作为掩模。 该装置被加热以驱动来自ASG层（23）的杂质，以使n + s掺杂多晶硅并形成n-FET源极和漏极（27,28）。 然后将硼注入到p-FET源极和漏极（25,26）中，ASG层用于从p型掺杂掩模多晶硅。 由于蚀刻的多晶硅未掺杂，因此获得了高精度的自对准。