公开(公告)号：WO1981001637A1

公开(公告)日：1981-06-11

申请号：PCT/US1980001527

申请日：1980-11-13

Applicant: NCR CORP

Inventor： NCR CORP ,  CHARI V

IPC: H03K13/00

CPC classification number: H04L25/4904

Abstract: A data recovery circuit (20) for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal (ENDATA). The data recovery circuit (20) includes a time delay circuit for delaying the PE pulse signal (ENDATA) by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal (CNTRL) that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal (ENDATA). The control signal (CNTRL) is used to generate a recovered clock signal (RCLK) by logically combining the control signal (CNTRL) with the PE pulse signal (ENDATA) and a one-half bit period delayed PE pulse signal (HBTD). The control signal (CNTRL) is also used to generate a recovered data signal (RDATA) by clocking the control signal (CNTRL) into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops.

公开(公告)号：WO1982000374A1

公开(公告)日：1982-02-04

申请号：PCT/US1981000901

申请日：1981-07-02

Applicant: NCR CORP

Inventor： NCR CORP ,  DUKE J ,  CHARI V

IPC: G06F13/00

CPC classification number: G06F13/22 ,  G06F13/124

Abstract: A data processing system including processing elements (22) and a central memory (10) has an input/output system for handling high data flow rates comprising an I/O processor (23) providing serial lines (31) to a plurality of peripheral subsystems (30), the I/O processor comprising a dynamic channel exchange coupling the serial lines to at least one serial channel processor (20). Processor (20) includes arithmetic logic means, a scratch-pad, a buffer for data transfer between the dynamic channel exchange and the central memory, and a control store having a plurality of routines for implementing a method of communication between the I/O processor and the peripheral subsystems. The method of communication involving polling the ith serial channel for a peripheral ready indication, establishing a message exchange for communication if a peripheral ready indication is detected, checking for a processor element request for communication with a peripheral subsystem, and providing a message exchange for an initial communication across the corresponding bit line to the peripheral subsystem.

Abstract translation: 包括处理元件（22）和中央存储器（10）的数据处理系统具有用于处理高数据流速的输入/输出系统，其包括向多个外围子系统提供串行线（31）的I / O处理器（23） （30），所述I / O处理器包括将串行线耦合到至少一个串行信道处理器（20）的动态信道交换。 处理器（20）包括算术逻辑装置，暂存器，用于在动态信道交换机和中央存储器之间进行数据传输的缓冲器，以及控制存储器，具有用于实现I / O处理器之间的通信方法的多个例程 和外围子系统。 涉及轮询第i个串行通道以进行外设就绪指示的通信方法，如果检测到外设准备就绪指示，则建立通信的消息交换，检查处理器元件与外围子系统通信的请求，以及为外部子系统提供消息交换 初始通信到相应的位线到外围子系统。

公开(公告)号：WO1982000373A1

公开(公告)日：1982-02-04

申请号：PCT/US1981000902

申请日：1981-07-02

Applicant: NCR CORP

Inventor： NCR CORP ,  COSTA J ,  CHARI V

IPC: G06F03/00

CPC classification number: G06F13/385 ,  G06F13/22

Abstract: A data processing system including processing elements (22) and a central memory (10) has an input/output system for handling high data transmission rates comprising an I/O processor (23) providing serial lines (31) to a plurality of peripheral subsystems (30) each of which comprises a peripheral adapter (40) and a plurality of peripheral devices (41), the peripheral adapter including a first means providing serial/parallel data conversion from the serial line (31), a second means providing control functions and information transfer to the peripheral devices, and third means for responding to the I/O processor in accordance with a message protocol. The message protocol involves interrogating an input signal indicating the end of a message from I/O processor (23), determining the message type, transmitting a response message and causing the peripheral adapter to enter an operating state which may involve further exchange of messages with the I/O processor.

Abstract translation: 包括处理元件（22）和中央存储器（10）的数据处理系统具有用于处理高数据传输速率的输入/输出系统，其包括向多个外围子系统提供串行线（31）的I / O处理器（23） （30），每个包括外围适配器（40）和多个外围设备（41），所述外围适配器包括从串行线路（31）提供串行/并行数据转换的第一装置，提供控制功能的第二装置 以及信息传送到外围设备，以及第三装置，用于根据消息协议响应I / O处理器。 消息协议包括询问指示来自I / O处理器（23）的消息结束的输入信号，确定消息类型，发送响应消息并使得外围适配器进入操作状态，这可能涉及进一步交换消息 I / O处理器。

公开(公告)号：AU7415481A

公开(公告)日：1982-02-16

申请号：AU7415481

申请日：1981-07-02

Applicant: NCR CORP

Inventor： CHARI V ,  COSTA J L

IPC: G06F9/22 ,  G06F3/00 ,  G06F13/22 ,  G06F13/38 ,  H04L69/14

Abstract: A data processing system including processing elements (22) and a central memory (10) has an input/output system for handling high data transmission rates comprising an I/O processor (23) providing serial lines (31) to a plurality of peripheral subsystems (30) each of which comprises a peripheral adapter (40) and a plurality of peripheral devices (41), the peripheral adapter including a first means providing serial/parallel data conversion from the serial line (31), a second means providing control functions and information transfer to the peripheral devices, and third means for responding to the I/O processor in accordance with a message protocol. The message protocol involves interrogating an input signal indicating the end of a message from I/O processor (23), determining the message type, transmitting a response message and causing the peripheral adapter to enter an operating state which may involve further exchange of messages with the I/O processor.

公开(公告)号：AU7415381A

公开(公告)日：1982-02-16

申请号：AU7415381

申请日：1981-07-02

Applicant: NCR CORP

Inventor： CHARI V ,  DUKE J R

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/22 ,  H04L69/14

Abstract: A data processing system including processing elements (22) and a central memory (10) has an input/output system for handling high data flow rates comprising an I/O processor (23) providing serial lines (31) to a plurality of peripheral subsystems (30), the I/O processor comprising a dynamic channel exchange coupling the serial lines to at least one serial channel processor (20). Processor (20) includes arithmetic logic means, a scratch-pad, a buffer for data transfer between the dynamic channel exchange and the central memory, and a control store having a plurality of routines for implementing a method of communication between the I/O processor and the peripheral subsystems. The method of communication involving polling the ith serial channel for a peripheral ready indication, establishing a message exchange for communication if a peripheral ready indication is detected, checking for a processor element request for communication with a peripheral subsystem, and providing a message exchange for an initial communication across the corresponding bit line to the peripheral subsystem.