公开(公告)号：WO1982002130A1

公开(公告)日：1982-06-24

申请号：PCT/US1981001666

申请日：1981-12-15

Applicant: NCR CORP

Inventor： NCR CORP ,  COOK DONALD M

IPC: H04L27/22

CPC classification number: H04L7/0066

Abstract: In order to recover the clock signal from a Manchester encoded serial data stream which is resistant to phase variations arising between the data bit signals in the data stream, the data stream is delayed by a one-quarter bit period and a three-quarter bit period to provide signals (QBT, TQBT) which are combined in a circuit (1, 2, 3) to provide a clock signal (RF). The circuit includes a latch (1) which is actuated by signals (QBT, TQBT) and a signal (LLF) representing decoded data combined in logic gates (2) and applied to the inputs of the latch.

Abstract translation: 为了从曼彻斯特编码的串行数据流恢复时钟信号，该串行数据流对数据流中的数据位信号之间产生的相位变化具有抵抗性，数据流被延迟四分之一位周期和四分之三位位周期 提供组合在电路（1,2,3）中以提供时钟信号（RF）的信号（QBT，TQBT）。 电路包括由信号（QBT，TQBT）和表示在逻辑门（2）中组合的解码数据的信号（LLF）启动并被施加到锁存器的输入端的锁存器（1）。