公开(公告)号：WO1981001758A1

公开(公告)日：1981-06-25

申请号：PCT/US1980001597

申请日：1980-11-26

Applicant: NCR CORP

Inventor： NCR CORP ,  OOSTERBAAN D ,  WILLIAMS G

IPC: G06F03/00

CPC classification number: G06F17/30949

Abstract: Hashing of a key data signal is accomplished by utilizing a pseudo-random number signal generator (22, 24, 26, 28 and 30) for generating a randomized signal in response to shift signals and the key data signals and an output register (32) for serially receiving the generated pseudo-random signal and for providing segments of the serially-received signal at its output. A counting circuit (36, 56) responsive to a preselected number of shift signals provides an output valid signal when the preselected number of shift signals has occurred and further shifts the pseudo-random number signal generator an amount corresponding to the preselected number of shift signals. The pseudo-random number signal generator includes a pair of cross-coupled shift registers (26, 28). The method of hashing the key data utilizes the steps of presetting the pseudo-random number generator and the counting circuit to an initialized state. The counting circuit is then loaded with a predetermined count whereupon key data is entered into the pseudo-random number generator so as to randomize the key data. A valid signal is provided when a block of key data has been hashed and the steps of entering the key data and providing a valid signal upon the occurrence of each block of key data is repeated until all key data blocks have been hashed.

公开(公告)号：WO1980002349A1

公开(公告)日：1980-10-30

申请号：PCT/US1980000364

申请日：1980-04-04

Applicant: NCR CORP

Inventor： NCR CORP ,  OOSTERBAAN D ,  WILLIAMS G

IPC: H04L09/02

CPC classification number: H04L9/0662 ,  H04L9/0637 ,  H04L2209/12 ,  H04L2209/34

Abstract: Enciphering/deciphering apparatus having two pseudo-random bit generators (16, 28) which are cross-coupled in the enciphering mode by logic circuitry (10, 14, 18, 20, 22, 26). An input data signal is directed to the input of each bit generator by a pair of summing devices (18, 20). The data signal is also logically combined with the output of each bit generator by a second pair of summing devices (30, 32). In the deciphering mode the pseudo-random bit generators are connected in a feedback configuration by logic circuitry (12, 14, 18, 20, 24, 26). The to-be-decoded signal is directed to the input of each bit generator by the first pair of summing devices (18, 20). The to-be-decoded signal is also logically combined with the output of each bit generator by the second pair of summing devices (30, 32) to provide the decoded signal.

Abstract translation: 具有通过逻辑电路（10,14,18,20,22,26）以加密模式交叉耦合的两个伪随机位发生器（16,28）的加密/解密装置。 输入数据信号通过一对求和装置（18,20）指向每个位发生器的输入。 数据信号还通过第二对求和装置（30,32）与每个位发生器的输出逻辑地组合。 在解密模式中，伪随机位发生器通过逻辑电路（12,14,18,20,24,26）以反馈配置连接。 被解码的信号被第一对求和装置（18,20）引导到每个位发生器的输入端。 待解码信号还通过第二对求和装置（30,32）与每个位发生器的输出逻辑地组合以提供解码信号。